Shallow trench isolation structure and semiconductor device with the same
A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.
1. A semiconductor device, comprising:
a substrate;
two shallow trench isolation disposed within the substrate, wherein each of the shallow trench isolation having multi-stacked layers and a groove being defined between layers of the multi-stacked layers, wherein the layers of the multi-stacked layers comprise a first dielectric layer, a second dielectric layer and a third dielectric layer stacked from bottom to top, and a topmost surface of the third dielectric layer is lower than a topmost surface of the substrate and is higher than a topmost surface of the first dielectric layer; and
a gate structure disposed on the substrate, partially across each of the shallow trench isolations, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer, and a portion of the gate electrode layer fills up the groove.
2. The semiconductor device according to claim 1 , wherein two opposite sidewalls of the gate structure are respectively disposed on the shallow trench isolations.
3. The semiconductor device according to claim 1 , wherein the topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the topmost surface of the substrate.
4. The semiconductor device according to claim 3 , wherein a lowest point of a top surface of the third dielectric layer is lower than the topmost surface of the second dielectric layer and is higher than the topmost surface of the first dielectric layer.
5. The semiconductor device according to claim 1 , wherein the gate dielectric layer is only disposed on an inner surface of the groove.
6. The semiconductor device according to claim 3 , wherein the gate dielectric layer is disposed on an inner surface of the groove and surfaces of the substrate.
7. The semiconductor device according to claim 1 , wherein the gate electrode layer comprises a polysilicon layer, and the polysilicon layer directly contacts the second dielectric layer and the third dielectric layer.
8. A semiconductor device, comprising:
a substrate;
two shallow trench isolation disposed within the substrate, wherein each of the shallow trench isolation having multi-stacked layers and a groove being defined between layers of the multi-stacked layers, wherein the layers of the multi-stacked layers comprises a first dielectric layer, a second dielectric layer and a third dielectric layer stacked from bottom to top, and a topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and a topmost surface of the substrate, and a lowest point of a top surface of the third dielectric layer is lower than the topmost surface of the second dielectric layer and is higher than the topmost surface of the first dielectric layer; and
a gate structure disposed on the substrate, partially across each of the shallow trench isolations, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer, and a portion of the gate electrode layer fills up the groove.