Method and system for resolving UNI port information on an external SOC/switch based on a mac-table cache
The present invention provides a method of using a mac-table cache to resolve UNI port information on an external system of chip (SOC) is provide. The method comprises, receiving, by a packet processing chip, a packet with a source address (SA); locating, by the packet processing chip, the SA in a mac-table cache implemented on the packet processing chip; and looking up a SOC mac-table implemented on the external SOC if the SA cannot be found in the mac-table cache.
1. A method of using a mac-table cache to resolve UNI port information on an external system on chip (SOC), comprising:
receiving, by a packet processing chip, a packet with a source address (SA);
determining whether the SA is stored in a mac-table cache implemented on the packet processing chip;
in response to determining that the SA is not stored in the mac-table cache, determining from a SOC mac-table implemented on the external SOC processing data for the SA stored in the SOC mac-table cache; and
updating the mac-table cache implemented on the packet processing chip via the SOC mac-table;
wherein the mac-table cache is implemented as an ASIC (application-specific integrated circuit);
wherein the method further comprising the steps of:
providing a co-location device (CO), the packet processing chip and the external SOC/switch to be connectively cascaded in a series, wherein the co-location device only connects to the packet processing chip; and
sending the packet from the external SOC or from a co-location device (CO) connected to the packet processing chip.
2. The method according to claim 1 , wherein the packet processing chip processes the packet based on the SA found in the mac-table cache.
3. A system in which a mac-table cache is used to resolve UNI port information, comprising:
a packet processing chip with a mac-table cache implemented thereon;
an external system on chip (SOC) with a SOC mac-table implemented thereon, electrically connected with the packet processing chip; and
a co-location device (CO), electrically connected with the packet processing chip;
wherein the packet processing chip is operatively configured to receive a packet with a source address (SA), determine whether the SA is stored in the mac-table cache, and obtain processing data from the SOC mac-table if the SA of the packet is not stored in the mac-table cache;
wherein the packet processing chip is further operatively configured, in response to determining that the SA is not stored in the mac-table cache, to determine from the SOC mac-table implemented on the external SOC processing data for the SA stored in the SOC mac-table cache, and updating the mac-table cache implemented on the packet processing chip via the SOC mac-table;
wherein the mac-table cache is implemented as an ASIC (application-specific integrated circuit) inside the packet processing chip;
wherein the co-location device (CO), the packet processing chip and the external SOC are connectively cascaded in a series, and the co-location device only connects to the packet processing chip, and operatively configured such that the packet processing chip receives the packet from the external SOC or from the co-location device (CO).
4. The system according to claim 3 , wherein the packet processing chip is further configured to process the packet based on the SA stored in the mac-table cache.