Super-junction based vertical gallium nitride JFET power devices
A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type; forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type; forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth; epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type; forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity type.
1. A vertical junction field effect transistor (JFET) device comprising:
a III-nitride substrate having a first conductivity type;
a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a plurality of trenches;
a second III-nitride structure formed within the trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type;
a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions;
a III-nitride gate layer formed within the recess regions and coupled to the second III-nitride structure, wherein the III-nitride gate layer is characterized by the second conductivity type;
a source metal layer coupled to an upper portion of each of the plurality of III-nitride fins; and
a gate metal layer coupled to an upper portion of the III-nitride gate layer.
2. The vertical JFET device of claim 1 wherein a dopant concentration of the plurality of III-nitride fins is greater than the dopant concentration of the first III-nitride layer.
3. The vertical JFET device of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.
4. The vertical JFET device of claim 1 wherein a depth of the plurality of trenches extend an entire thickness of the first III-nitride layer.
5. The vertical JFET device of claim 1 wherein the III-nitride gate layer is coupled to a portion of the first III-nitride layer.
6. The vertical JFET device of claim 1 wherein the III-nitride gate layer comprises an epitaxially regrown layer.
7. The vertical JFET device of claim 1 wherein the III-nitride gate layer comprises a deposited layer disposed on the second III-nitride structure.
8. The vertical JFET device of claim 1 wherein the III-nitride gate layer comprises an ion implanted layer or diffused dopant layer.
9. The vertical JFET device of claim 8 wherein the III-nitride gate layer comprises:
a first portion extending partially up sidewalls of the plurality of III-nitride fins;
a second portion extending across a portion of the first III-nitride layer; and
a third portion extending across a top surface of the second III-nitride structure.
10. The vertical JFET device of claim 9 wherein the first portion of the III-nitride gate layer is characterized by a height amounting to 70%-90% of a thickness of the plurality of III-nitride fins.