Tracking debug events from an autonomous module through a data pipeline
A method for debugging a software program is provided when the software program is executed on a processor. An asynchronous debug event is detected. The asynchronous debug event is tracked through a data pipeline to the processor. In one embodiment, the asynchronous debug event is acted on only when the processor is ready to consume a data element associated with the asynchronous debug event.
1. A device comprising:
a processor core; and
a data retrieval circuit coupled to the processor core and configured to couple to a cache memory, wherein the data retrieval circuit includes:
an address generator that includes a set of loop counters, wherein the address generator is configured to use the set of loop counters to generate a set of memory addresses in response to an instruction; and
debug event detection circuitry coupled to the address generator that includes:
a count memory configured to store a respective count value for each counter of the set of loop counters; and
comparator circuitry coupled to the set of loop counters and to the count memory and configured to:
compare a current count of a respective counter of the set of loop counters to the respective count value in the count memory; and
generate a debug event based on the comparison of the current count to the respective count value.
2. The device of claim 1 , wherein the data retrieval circuit further includes:
a data buffer configured to store a set of data elements retrieved from the cache memory based on the set of memory addresses, wherein a first data element of the set of data elements is associated with the debug event; and
a debug event buffer configured to store the debug event such that the debug event propagates through the debug event buffer as the first data element propagates through the data buffer.
3. The device of claim 2 , wherein the data retrieval circuit is configured to provide the debug event to the processor core in response to a read request for the first data element.
4. The device of claim 2 , wherein each of the data buffer and the debug event buffer is structured as a first-in-first-out buffer.
5. The device of claim 1 , wherein the count memory is configured to store a range of count values for a counter of the set of loop counters.
6. The device of claim 1 , wherein the processor core is configured to process the debug event as a breakpoint.
7. The device of claim 1 , wherein the processor core is configured to process the debug event as a probe point.
8. The device of claim 1 , wherein the cache memory is a level-two cache memory and the data retrieval circuit is configured to couple to the level-two cache memory via a data path that does not include a level-one cache memory.
9. A device comprising:
a processor core; and
a data retrieval circuit coupled to the processor core and configured to couple to a cache memory, wherein the data retrieval circuit includes:
an address generator that includes a set of loop counters, wherein the address generator is configured to use the set of loop counters to generate a set of memory addresses in response to an instruction; and
debug event detection circuitry coupled to the address generator that includes:
a count memory configured to store a respective count value for each counter of the set of loop counters;
comparator circuitry coupled to the set of loop counters and to the count memory and configured to:
compare a current count of a respective counter of the set of loop counters to the respective count value in the count memory; and
generate a debug event based on the comparison of the current count to the respective count value; and
a loop bypass memory configured to store a respective bypass indication for each counter of the set of loop counters;
wherein the comparator circuitry is configured to determine whether to generate the debug event based on the comparison of the current count of a respective counter of the set of loop counters to the respective count value based on the respective bypass indication.
10. The device of claim 9 , wherein the comparator circuitry includes:
a set of comparators coupled to the set of loop counters and to the count memory;
a set of OR gates coupled to the set of comparators and to the loop bypass memory; and
an AND gate coupled to the set of OR gates.
11. The device of claim 9 , wherein the comparator circuitry includes:
a set of comparators coupled to the set of loop counters and to the count memory; and
a multiplexer coupled to the loop bypass memory and to the set of comparators.
12. A device comprising:
a processor core;
a memory; and
a streaming engine coupled between the processor core and the memory, wherein the streaming engine includes:
an address generator that includes a set of loop counters to generate a set of memory addresses;
debug event detection circuitry coupled to the address generator that includes:
a count memory configured to store a respective count value for each counter of the set of loop counters; and
comparator circuitry coupled to the set of loop counters and to the count memory and configured to:
compare a current count of a respective counter of the set of loop counters to the respective count value in the count memory; and
generate a debug event based on the comparison of the current count to the respective count value;
a memory interface coupled to the memory and configured to retrieve a data set based on the set of memory addresses, wherein the debug event is associated with a first data element of the data set;
a data buffer configured to store the data set; and
a debug event buffer configured to store the debug event such that the debug event is aligned with the first data element.
13. The device of claim 12 , wherein the streaming engine is configured to provide the debug event to the processor core in response to a read request for the first data element.
14. The device of claim 12 , wherein the data buffer and the debug event buffer are each structured as a first-in-first-out buffer.
15. The device of claim 12 , wherein:
the debug event detection circuitry further includes a loop bypass memory configured to store a respective bypass indication for each counter of the set of loop counters; and
the comparator circuitry is configured to determine whether to generate the debug event based on the comparison of the current count of a respective counter of the set of loop counters to the respective count value based on the respective bypass indication.
16. The device of claim 15 , wherein the comparator circuitry includes:
a set of comparators coupled to the set of loop counters and to the count memory;
a set of OR gates coupled to the set of comparators and to the loop bypass memory; and
an AND gate coupled to the set of OR gates.
17. The device of claim 15 , wherein the comparator circuitry includes:
a set of comparators coupled to the set of loop counters and to the count memory; and
a multiplexer coupled to the loop bypass memory and to the set of comparators.
18. The device of claim 12 , wherein the count memory is configured to store a range of count values for each counter of the set of loop counters.
19. The device of claim 12 , wherein the processor core is configured to process the debug event as a breakpoint or a probe point.
20. The device of claim 12 , wherein the memory is a level-two cache memory and the streaming engine is coupled to the level-two cache memory via a data path that does not include a level-one cache memory.