Semiconductor device with fine metal lines for BEOL structure and method of manufacturing the same

1. A semiconductor device comprising a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure,

wherein the FEOL structure comprises at least one source/drain region and at least one gate structure, and

wherein the BEOL structure comprises:

a plurality of 1 st fine metal lines arranged in a row at a same pitch, each of the plurality of 1 st fine metal lines having a same width;

at least one 1 st wide metal line formed at a side of the plurality of 1 st fine metal lines, the 1 st wide metal line having a width greater than the width of the 1 st fine metal line;

a 2 nd fine metal line at a side of the 1 st wide metal line opposite to the 1 st fine metal lines; and

a 3 rd fine metal line at a side of the 2 nd fine metal line opposite to the 1 st wide metal line,

wherein no other metal lines are present between the 2 nd fine metal line and the 3 rd fine metal line at a same level,

wherein a width of a space between the 2 nd fine metal line and the 3 rd fine metal line is greater than the width of the space between the two adjacent 1 st fine metal lines, and

wherein each of the plurality of 1 st fine metal lines comprises a material different from a material included in the 1 st wide metal line.

2. The semiconductor device of claim 1 , wherein the width of the 1 st wide metal line is greater than twice the width of the 1 st fine metal line.

3. The semiconductor device of claim 1 , wherein the width of the 1 st wide metal line is equal to a sum of twice the width of the 1 st fine metal line and a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.

4. The semiconductor device of claim 1 , wherein a width of a space between the 1 st wide metal line and a 1 st fine metal line, among the plurality of 1 st fine metal lines, adjacent to the 1 st wide metal line is equal to a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.

5. The semiconductor device of claim 4 ,

wherein a width of the 2 nd fine metal line is equal to the width of the 1 st fine metal line,

wherein the width of the space between the 1 st wide metal line and the 1 st fine metal line adjacent to the 1 st wide metal line is equal to a width of a space between the 1 st wide metal line and the 2 nd fine metal line.

6. The semiconductor device comprising of claim 1 , further comprising a middle-of-line (MOL) structure, the MOL structure comprising:

at least one source/drain contact structure connecting the source/drain region to at least one of the plurality of 1 st fine metal lines; and

at least one gate contact structure connecting the gate structure to another at least one of the plurality of 1 st fine metal lines,

wherein the at least one 1 st wide metal line is connected to a power source.

7. The semiconductor device of claim 6 , wherein the width of the 1 st wide metal line is equal to a sum of twice the width of the 1 st fine metal line and a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.

8. The semiconductor device of claim 6 , wherein a width of a space between the 1 st wide metal line and a 1 st fine metal line, among the plurality of 1 st fine metal lines, adjacent to the 1 st wide metal line is equal to a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.

9. The semiconductor device of claim 8 , wherein the plurality of 1 st fine metal lines are formed by at least one of atomic layer deposition (ALD) and conformal chemical vapor deposition (CVD), and the 1 st wide metal line is formed by a physical vapor deposition (PVD).

10. A semiconductor device comprising a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure,

wherein the FEOL structure comprises at least one source/drain region and at least one gate structure, and

wherein the BEOL structure comprises:

a plurality of 1 st fine metal lines arranged in a row with a same pitch, each of the plurality of 1 st fine metal lines having a same width;

at least one 1 st wide metal line formed at a side of the plurality of 1 st fine metal lines, the 1 st wide metal line having a width greater than the width of the 1 st fine metal line;

a 2 nd fine metal line at a side of the 1 st wide metal line opposite to the 1 st fine metal lines; and

a 3 rd fine metal line at a side of the 2 nd fine metal line opposite to the 1 st wide metal line,

wherein no other metal lines are present between the 2 nd fine metal line and the 3 rd fine metal line at a same level,

wherein a width of a space between the 2 nd fine metal line and the 3 rd fine metal line is greater than the width of the space between the two adjacent 1 st fine metal lines, and

wherein the width of the 1 st wide metal line is greater than twice the width of the 1 st fine metal line.

11. The semiconductor device of claim 10 , wherein the width of the 1 st wide metal line is equal to a sum of twice the width of the 1 st fine metal line and a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.

12. The semiconductor device of claim 10 , wherein each of the plurality of 1 st fine metal lines comprises a material different from a material included in the 1 st wide metal line.

13. The semiconductor device of claim 12 , wherein the width of the 1 st wide metal line is equal to a sum of twice the width of the 1 st fine metal line and a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.

14. The semiconductor device of claim 12 , wherein a width of a space between the 1 st wide metal line and a 1 st fine metal line, among the plurality of 1 st fine metal lines, adjacent to the 1 st wide metal line is equal to a width of a space between two adjacent 1 st fine metal lines among the plurality 1 st fine metal lines.