Memory device including double PN junctions and driving method thereof, and capacitor-less memory device including double PN junctions and control gates and operation method thereof
A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.
1. A memory device including a double PN junction, comprising:
at least one semiconductor layer having a double PN junction; and
an anode and a cathode which simultaneously contact the semiconductor layer,
wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction, and
wherein the semiconductor layer is an NPN-type semiconductor layer, an N-type semiconductor layer of the NPN-type semiconductor layer is low concentration, and the other N-type semiconductor layer of the NPN-type semiconductor layer is high concentration.
2. The memory device including a double PN junction according to claim 1 , wherein the NPN-type semiconductor layer comprises the N-type semiconductor layer, a P-type semiconductor layer, and the other N-type semiconductor layer.
3. The memory device including a double PN junction according claim 1 , wherein the low concentration N-type semiconductor layer contacts the anode, and the high concentration N-type semiconductor layer contacts the cathode.
4. The memory device including a double PN junction according to claim 3 , wherein a junction between the anode and the low concentration N-type semiconductor layer is the Schottky junction, and a junction between the high concentration N-type semiconductor layer and the cathode is the Ohmic junction.
5. A memory device array comprising the memory device according to claim 1 as a unit device.
6. An operation method of a memory device including a double PN junction, comprising:
applying a program voltage to the memory device;
lowering resistance of at least one semiconductor layer by lowering a potential barrier of the double PN junction by the program voltage to move carriers to the semiconductor layer; and
reading the resistance of the semiconductor layer,
wherein the memory device comprises:
the semiconductor layer having the double PN junction; and
an anode and a cathode which simultaneously contact the semiconductor layer, and
wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction.
7. The operation method of a memory device according to claim 6 , further comprising:
after lowering the resistance of the semiconductor layer,
increasing the resistance of the semiconductor layer by selectively applying an erase voltage to the memory device.
8. The operation method of a memory device according to claim 7 , further comprising:
after applying the program voltage,
re-lowering the resistance of the semiconductor layer by selectively re-applying a refresh voltage to the memory device.
9. A capacitor-less memory device including a double PN junction and a control gate, comprising:
at least one semiconductor layer having a double PN junction;
a control gate which contacts the semiconductor layer; and
an anode and a cathode which simultaneously contact the semiconductor layer,
wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction,
wherein the semiconductor layer is an NPN-type semiconductor layer, an N-type semiconductor layer of the NPN-type semiconductor layer is low concentration, and the other N-type semiconductor layer of the NPN-type semiconductor layer is high concentration, and
wherein the low concentration N-type semiconductor layer contacts the anode, and the high concentration N-type semiconductor layer contacts the cathode.
10. A memory device array comprising the capacitor-less memory device according to claim 9 as a unit device.
11. An operation method of the capacitor-less memory device including a double PN junction and a control gate according to claim 9 , the operation method comprising:
applying a program voltage to the capacitor-less memory device;
lowering resistance of the semiconductor layer by lowering a potential barrier of the double PN junction by the program voltage to move carriers to the semiconductor layer; and
reading the resistance of the semiconductor layer.
12. The operation method of a capacitor-less memory device according to claim 11 , further comprising:
after lowering the resistance of the semiconductor layer,
increasing the resistance of the semiconductor layer by selectively applying an erase voltage to the capacitor-less memory device.
13. The operation method of a capacitor-less memory device according to claim 11 , further comprising:
inhibiting, by the control gate, an operation error of an unselected cell in a memory cell array configuration formed using the capacitor-less memory device.