IP Library Granted Patent US 11,961,823
Granted Patent B1
US 11,961,823 · App. 17/354,927 · Granted Apr 16, 2024

Forming and/or configuring stacked dies

Inventors: Praful Jain (San Jose, CA); Martin Voogel (Niwot, CO); Brian Gaide (Erie, CO)
Assignee: XILINX, INC.
H01L25/0657H01L24/16H01L2224/16145H01L2225/06513H01L2924/15311
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Quick Facts
Patent No.
US 11,961,823
App. No.
17/354,927
Granted
Apr 16, 2024
Kind
B1
Abstract

Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two or more of the dies that are interchangeable are based on the characteristics.

Claims (11)

1. A method of implementing a multi-chip device, the method comprising:

determining whether segments of interchangeable dies in a die stack are functional, N number of the interchangeable dies being in the die stack, segments that align in the interchangeable dies forming respective slivers; and

configuring the interchangeable dies into M number of logical dies when each sliver includes at least the M number of segments that are functional, the M number being less than the N number, wherein configuring the interchangeable dies into the M number of the logical dies further includes activating segments of each sliver that includes more than the M number of segments that are functional based on a projected temperature of the die stack, a projected static power of the die stack, a projected performance of the die stack, or a combination thereof.

2. The method of claim 1 , wherein activating segments of each sliver that includes more than the M number of segments that are functional is based on a projected junction temperature of the die stack.

3. The method of claim 1 , wherein activating segments of each sliver that includes more than the M number of segments that are functional is based on the projected static power of the die stack, segments in a respective sliver that minimize static power consumption being activated.

4. The method of claim 1 , wherein activating segments of each sliver that includes more than the M number of segments that are functional is based on the projected performance of the die stack, segments in a respective sliver that are capable of faster operation being activated.

5. The method of claim 1 further comprising:

determining characteristics of the interchangeable dies; and

forming the die stack, respective placements within the die stack of the interchangeable dies being based on the characteristics.

6. The method of claim 5 , wherein the characteristics include respective projected amounts of leakage current of the interchangeable dies, the interchangeable dies being placed within the die stack in an order of decreasing projected amounts of leakage current from a placement of a heat dissipation element.

7. The method of claim 1 , wherein each of the interchangeable dies includes a programmable integrated circuit comprising respective segments, the segments of the programmable integrated circuit including respective segments of a programmable logic region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2021
From: JAIN, PRAFUL; VOOGEL, MARTIN; GAIDE, BRIAN
To: XILINX, INC.
Reel/Frame 056900/0705 →
Cited By (4)
US 12,362,320 US 12,388,048 US 12,406,127 US 12,469,823