IP Library › Granted Patent US 12,362,320
Granted Patent B2
US 12,362,320 · App. 18/367,423 · Granted Jul 15, 2025

Semiconductor package structure

Inventors: Chien-Chi Lee (Kaohsiung, TW); Jyan-Ann Hsia (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L25/0652H01L2225/06506H01L2225/06513H01L2225/06517H01L2225/0652H01L2225/06527
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Quick Facts
Patent No.
US 12,362,320
App. No.
18/367,423
Granted
Jul 15, 2025
Kind
B2
Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.

Claims (29)

1. A semiconductor package structure, comprising:

a first electronic component;

a second electronic component disposed above the first electronic component;

a third electronic component spaced apart from the first electronic component;

a fourth electronic component disposed above the third electronic component;

a connection element electrically connecting the second electronic component to the fourth electronic component;

a carrier; and

a first storage element and a second storage element disposed over the carrier, wherein an elevation of a top surface of the first storage element and an elevation of a top surface of the second storage element are higher than an elevation of a top surface of the second electronic component with respect to a surface of the carrier;

wherein the second electronic component comprises a first processing element, the fourth electronic component comprises a second processing element, and the connection element is configured to adjust bandwidths of a plurality of transmission paths between the first electronic component, the second electronic component, the third electronic component, and the fourth electronic component.

2. The semiconductor package structure as claimed in claim 1 , wherein the connection element comprises a first transmission path and a second transmission path substantially perpendicular to the first transmission path.

3. The semiconductor package structure as claimed in claim 1 , further comprising a storage element overlapping the connection element and the second electronic component in a direction substantially parallel to the top surface of the second electronic component.

4. The semiconductor package structure as claimed in claim 1 , further comprising a storage element overlapping a transmission path of the connection element in a direction substantially parallel to the top surface of the second electronic component.

5. The semiconductor package structure as claimed in claim 1 , wherein the first storage element and the second storage element are at two opposite lateral sides of the second electronic component.

6. The semiconductor package structure as claimed in claim 1 , wherein the fourth electronic component is disposed between the first storage element and the second storage element.

7. The semiconductor package structure as claimed in claim 6 , wherein the elevation of the top surface of the first storage element and the elevation of the top surface of the second storage element is higher than an elevation of a top surface of the fourth electronic component with respect to the surface of the carrier.

8. The semiconductor package structure as claimed in claim 1 , wherein the second electronic component at least partially overlaps the connection element in a direction substantially perpendicular to the top surface of the second electronic component.

9. The semiconductor package structure as claimed in claim 1 , further comprising a fifth electronic component adjacent to the fourth electronic component, wherein the fifth electronic component comprises a third processing element.

10. A semiconductor package structure, comprising:

a first electronic component;

a second electronic component comprising a first I/O module and disposed above the first electronic component;

a third electronic component spaced apart from the first electronic component;

a connection element electrically connected to the second electronic component; and

a first storage element and a second storage element, wherein the second electronic component comprises a first processing element and is disposed between the first storage element and the second storage element,

a fourth electronic component between the first storage element and the second storage element, wherein the fourth electronic component comprises a second processing element, and an elevation of a top surface of the fourth electronic component is between an elevation of a top surface of the connection element and an elevation of a top surface of the first storage element;

wherein the first I/O module of the second electronic component comprises a controller configured to control data transmission between the second electronic component and the connection element.

11. The semiconductor package structure as claimed in claim 10 , wherein the connection element is between the first storage element and the second storage element.

12. The semiconductor package structure as claimed in claim 11 , wherein an elevation of a top surface of the second storage element is higher than the elevation of the top surface of the connection element with respect to a top surface of the first electronic component.

13. The semiconductor package structure as claimed in claim 10 , further comprising a fifth electronic component adjacent to the first storage element, wherein the fifth electronic component comprises a third processing element.

14. The semiconductor package structure as claimed in claim 13 , wherein the third processing element is disposed between the first storage element and the second storage element.

Continuity (2)
Continuation 17357851 · Jun 24, 2021
Related Publication 20230420416A1 · Dec 28, 2023
References Cited (17)
US 9761559B1 · Shih et al. · 2017 [cited by applicant]
US 11961823B1 · Jain · 2024 [cited by examiner]
US 12079475B1 · Mathuriya · 2024 [cited by examiner]
US 20170062383A1 · Yu et al. · 2017 [cited by applicant]
US 20190363715A1 · Lee et al. · 2019 [cited by applicant]
US 20200098724A1 · Liff · 2020 [cited by examiner]
US 20200144170A1 · Yazdani · 2020 [cited by applicant]
US 20200161242A1 · Lin et al. · 2020 [cited by applicant]
US 20200272564A1 · Keeth et al. · 2020 [cited by applicant]
US 20210296242A1 · Hossain · 2021 [cited by examiner]
US 20220028848A1 · Baek · 2022 [cited by examiner]
US 20220199556A1 · Zhou et al. · 2022 [cited by applicant]
US 20220359464A1 · Zaman · 2022 [cited by examiner]
US 20220399277A1 · Elsherbini · 2022 [cited by examiner]
Gupta et al., “Ultra-thin chips for high-performance flexible electronics”, npj Flexible Electronics (2018)2:8, 18 pages. [cited by applicant]
Non-Final Office Action for U.S. Appl. No. 17/357,851, issued Jan. 4, 2023, 16 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/357,851, issued May 3, 2023, 9 pages. [cited by applicant]