Field effect transistors including quantum layers
View Patent ↗Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region.
1. A field effect transistor, comprising:
a substrate;
an oxide layer disposed at least partially over the substrate;
a quantum layer disposed over the oxide layer and the substrate, adjacent the oxide layer, the quantum layer further comprising:
a first portion disposed directly over the substrate;
a second portion formed opposite the first portion, the second portion disposed directly over the oxide layer; and
an intermediate portion formed between the first portion and the second portion;
a drain region disposed directly over the substrate adjacent the quantum layer;
a source region disposed over the quantum layer, opposite the drain region;
a channel region formed over the quantum layer, between the drain region and the source region; and
a gate formed within the channel region, the gate disposed over the quantum layer.
2. The field effect transistor of claim 1 , wherein the channel region is formed adjacent and offset from the oxide layer.
3. The field effect transistor of claim 1 , wherein the oxide layer includes an angled section extending toward the substrate layer, and
the intermediate portion includes an angled surface substantially corresponding to the angled section of the oxide layer.
4. The field effect transistor of claim 1 , wherein the channel region is disposed directly over the first portion of the quantum layer.
5. The field effect transistor of claim 1 , wherein the source region is disposed directly over the second portion of the quantum layer.
6. A field effect transistor, comprising:
a substrate;
an oxide layer disposed at least partially over the substrate;
a quantum layer disposed over the oxide layer and the substrate, adjacent the oxide layer, the quantum layer further comprising:
a first portion disposed directly over the substrate;
a second portion formed opposite the first portion, the second portion disposed directly over the oxide layer; and
an intermediate portion formed between the first portion and the second portion;
a drain region disposed directly over the substrate adjacent the quantum layer; a source region disposed over the quantum layer, opposite the drain region; and
a channel region formed over the quantum layer, between the drain region and the source region, the channel region formed adjacent and offset from the oxide layer and further including:
an insulator layer disposed directly over the quantum layer, and
a top gate formed in the channel region and disposed directly over the insulator layer.
7. The field effect transistor of claim 6 , wherein the oxide layer includes an angled section extending toward the substrate layer, and the intermediate portion includes an angled surface substantially corresponding to the angled section of the oxide layer.
8. The field effect transistor of claim 7 , wherein the channel region is disposed directly over the first portion of the quantum layer.
9. The field effect transistor of claim 7 , wherein the source region is disposed directly over the second portion of the quantum layer.
10. A field effect transistor, comprising:
a substrate;
an oxide layer disposed at least partially over the substrate;
a quantum layer disposed over the oxide layer and the substrate, adjacent the oxide layer;
a drain region disposed directly over the substrate adjacent the quantum layer;
a source region disposed over the quantum layer, opposite the drain region; and a channel region formed over the quantum layer, between the drain region and the source region;
wherein the quantum layer further comprises:
a first portion disposed directly over the substrate;
a second portion formed opposite the first portion, the second portion disposed directly over the oxide layer; and
an intermediate portion formed between the first portion and the second portion; and
wherein the oxide layer includes an angled section extending toward the substrate layer, and the intermediate portion includes an angled surface substantially corresponding to the angled section of the oxide layer.
11. The field effect transistor of claim 10 , wherein the channel region is formed adjacent and offset from the oxide layer.
12. The field effect transistor of claim 11 , wherein the channel region further comprises:
an insulator layer disposed directly over the quantum layer; and
a top gate disposed directly over the insulator layer.
13. The field effect transistor of claim 11 , wherein the channel region is disposed directly over the first portion of the quantum layer.
14. The field effect transistor of claim 11 , wherein the source region is disposed directly over the second portion of the quantum layer.