Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environment
An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.
1. A processor comprising:
processing resources comprising execution circuitry to:
receive a fused secure hash algorithm (SHA) instruction identifying an opcode field identifying an opcode for the fused SHA instruction, a length field specifying a length value comprising a data size of the fused SHA instruction, an operation type field specifying a functional control value identifying an operation type of the fused SHA instruction, and source and destination operand fields, wherein the fused SHA instruction supports multiple sub-functions that each comprise multiple merged operations;
determine a sub-function of the multiple sub-functions of the fused SHA instruction based on a combination of the length value and the functional control value identified in the fused SHA instruction, wherein the multiple sub-functions each perform different combinations of operations that are merged for the fused SHA instruction, and wherein the multiple sub-functions comprising a first subset of message scheduling sub-functions and a second subset of compression sub-functions;
cause the sub-function to be scheduled to an integer pipeline of the execution circuitry; and
execute the sub-function of the fused SHA instruction in the integer pipeline of the execution circuitry, the sub-function to perform a set of the multiple merged operations on a source operand of the fused SHA instruction, wherein the integer pipeline of the execution circuitry comprises:
wiring to implement at least one of rotate operations or shift operations of the different combinations of the operations; and
xor circuitry to implement xor operations of the different combinations of the operations.
2. The processor of claim 1 , wherein the message scheduling sub-functions of the fused SHA instruction perform a message scheduling component of an SHA-2 algorithm.
3. The processor of claim 1 , wherein the compression sub-functions of the fused SHA instruction perform a compression component of an SHA-2 algorithm.
4. The processor of claim 1 , wherein the length value corresponds to the data size comprising at least one of 256 bits or 512 bits.
5. The processor of claim 1 , wherein the operation type comprises at least one of a message schedule operation or a compression operation.
6. The processor of claim 1 , wherein the fused SHA instruction identifies a single source operand comprising the source operand.
7. The processor of claim 1 , wherein the processor comprises a graphics processing unit (GPU).
8. The processor of claim 1 , wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.
9. A method comprising:
receiving, by an execution resource of a graphics processor, a fused secure hash algorithm (SHA) instruction identifying an opcode field identifying an opcode for the fused SHA instruction, a length field specifying a length value comprising a data size of the fused SHA instruction, an operation type field specifying a functional control value identifying an operation type of the fused SHA instruction, and source and destination operand fields, wherein the fused SHA instruction supports multiple sub-functions that each comprise multiple merged operations;
determining a sub-function of the multiple sub-functions of the fused SHA instruction based on a combination of the length value and the functional control value identified in the fused SHA instruction, wherein the multiple sub-functions each perform different combinations of operations that are merged for the fused SHA instruction, and wherein the multiple sub-functions comprising a first subset of message scheduling sub-functions and a second subset of compression sub-functions;
causing, by the execution resource, the sub-function to be scheduled to an integer pipeline of the execution resource; and
executing, by execution circuitry of the execution resource, the sub-function of the fused SHA instruction in the integer pipeline of the execution circuitry, the sub-function to perform a set of the multiple merged operations on a source operand of the fused SHA instruction, wherein the integer pipeline of the execution circuitry comprises:
wiring to implement at least one of rotate operations or shift operations of the different combinations of the operations; and
xor circuitry to implement xor operations of the different combinations of the operations.
10. The method of claim 9 , wherein the message scheduling sub-functions of the fused SHA instruction perform a message scheduling component of an SHA-2 algorithm.
11. The method of claim 9 , wherein the compression sub-functions of the fused SHA instruction perform a compression component of an SHA-2 algorithm.
12. The method of claim 9 , wherein the length value corresponds to the data size comprising at least one of 256 bits or 512 bits.
13. The method of claim 9 , wherein the operation type comprises at least one of a message schedule operation or a compression operation.
14. A system comprising:
a memory to store a block of data; and
a processor coupled to the memory, the processor comprising processing resources, the processing resources comprising execution circuitry to:
receive a fused secure hash algorithm (SHA) instruction identifying an opcode field identifying an opcode for the fused SHA instruction, a length field specifying a length value comprising a data size of the fused SHA instruction, an operation type field specifying a functional control value identifying an operation type of the fused SHA instruction, and source and destination operand fields, wherein the fused SHA instruction supports multiple sub-functions that each comprise multiple merged operations;
determine a sub-function of the multiple sub-functions of the fused SHA instruction based on a combination of the length value and the functional control value identified in the fused SHA instruction, wherein the multiple sub-functions each perform different combinations of operations that are merged for the fused SHA instruction, and wherein the multiple sub-functions comprising a first subset of message scheduling sub-functions and a second subset of compression sub-functions;
cause the sub-function to be scheduled to an integer pipeline of the execution circuitry; and
execute the sub-function of the fused SHA instruction in the integer pipeline of the execution circuitry, the sub-function to perform a set of the multiple merged operations on a source operand of the fused SHA instruction, wherein the integer pipeline of the execution circuitry comprises:
wiring to implement at least one of rotate operations or shift operations of the different combinations of the operations; and
xor circuitry to implement xor operations of the different combinations of the operations.
15. The system of claim 14 , wherein the message scheduling sub-functions of the fused SHA instruction perform a message scheduling component of an SHA-2 algorithm.
16. The system of claim 14 , wherein the compression sub-functions of the fused SHA instruction perform a compression component of an SHA-2 algorithm.
17. The system of claim 14 , wherein the length value corresponds to the data size comprising at least one of 256 bits or 512 bits, and wherein the operation type comprises at least one of a message schedule operation or a compression operation.
18. A non-transitory computer-readable storage medium having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
receiving, by an execution resource of a graphics processor comprising the one or more processors, a fused secure hash algorithm (SHA) instruction identifying an opcode field identifying an opcode for the fused SHA instruction, a length field specifying a length value comprising a data size of the fused SHA instruction, an operation type field specifying a functional control value identifying an operation type of the fused SHA instruction, and source and destination operand fields, wherein the fused SHA instruction supports multiple sub-functions that each comprise multiple merged operations;
determining a sub-function of the multiple sub-functions of the fused SHA instruction based on a combination of the length value and the functional control value identified in the fused SHA instruction, wherein the multiple sub-functions each perform different combinations of other operations that are merged for the fused SHA instruction, and wherein the multiple sub-functions comprising a first subset of message scheduling sub-functions and a second subset of compression sub-functions;
causing, by the execution resource, the sub-function to be scheduled to an integer pipeline of the execution resource; and
executing, by execution circuitry of the execution resource, the sub-function of the fused SHA instruction in the integer pipeline of the execution circuitry, the sub-function to perform a set of the multiple merged operations on a source operand of the fused SHA instruction, wherein the integer pipeline of the execution circuitry comprises:
wiring to implement at least one of rotate operations or shift operations of the different combinations of the operations; and
xor circuitry to implement xor operations of the different combinations of the operations.
19. The non-transitory computer-readable storage medium of claim 18 , wherein the message scheduling sub-functions of the fused SHA instruction perform a message scheduling component of an SHA-2 algorithm.
20. The non-transitory computer-readable storage medium of claim 18 , wherein the compression sub-functions of the fused SHA instruction perform a compression component of an SHA-2 algorithm.
21. The non-transitory computer-readable storage medium of claim 18 , wherein the length value corresponds to the data size comprising at least one of 256 bits or 512 bits, and wherein the operation type comprises at least one of a message schedule operation or a compression operation.