FLEXIBLE RETURN AND EVENT DELIVERY

1 . An apparatus comprising:

decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and

execution circuitry to execute the decoded single instruction according to the opcode to cause a return from an event handler while staying in a most privileged level and establish a return context that was in effect before event delivery.

2 . The apparatus of claim 1 , wherein the execution of the decoded instruction is to not modify segment registers.

3 . The apparatus of claim 1 , wherein the opcode is F2 0F 01 CA.

4 . The apparatus of claim 1 , wherein the most privileged level is ring 0.

5 . The apparatus of claim 1 , wherein to execute the decode instruction the execution circuitry is to load and check the return context from a stack.

6 . The apparatus of claim 5 , wherein the execution circuitry is to check a shadow stack to confirm validity of the return.

7 . The apparatus of claim 5 , wherein the execution circuitry is to establish the return context by, at least in part, loading one or more registers.

8 . A method comprising:

decoding a single instruction, the single instruction to include a field for an opcode; and

executing the decoded instruction according to the opcode to cause a return from an event handler while staying in a most privileged level and establish a return context that was in effect before event delivery.

9 . The method of claim 8 , wherein executing the decoded instruction further comprises not modifying segment registers.

10 . The method of claim 8 , wherein the opcode is F2 0F 01 CA.

11 . The method of claim 8 , wherein the most privileged level is ring 0.

12 . The method of claim 8 , wherein the executing further comprises loading and checking the return context from a stack.

13 . The method of claim 12 , wherein the executing is to check a shadow stack to confirm validity of the return.

14 . The method of claim 12 , wherein the executing is to establish the return context by, at least in part, loading one or more registers.

15 . A method comprising:

translating a single instruction from a first instruction set architecture into one or more instructions of a second instruction set architecture, the single instruction having a field for an opcode, the opcode indicating that execution circuitry is to cause a return from an event handler while staying in a most privileged level and establish a return context that was in effect before event delivery;

decoding the one or more instructions of the second instruction set architecture; and

executing the decoded one or more instructions of the second instruction set architecture to cause a return from an event handler while staying in a most privileged level and establish a return context that was in effect before event delivery.

16 . The method of claim 15 , wherein the opcode is F2 0F 01 CA.

17 . The method of claim 15 , wherein the most privileged level is ring 0.

18 . A system comprising:

a processor core including:

decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, and

execution circuitry to execute the decoded single instruction according to the opcode to cause a return from an event handler while staying in a most privileged level and establish a return context that was in effect before event delivery; and

memory coupled to the processor core to store the single instruction.

19 . The system of claim 18 , wherein the opcode is F2 0F 01 CA.

20 . The system of claim 18 , wherein the execution circuitry is to establish the return context by, at least in part, loading one or more registers.

21 . An apparatus comprising:

decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and

execution circuitry to execute the decoded instruction according to the opcode to cause a return from an event handler while transitioning to a least privileged ring and establishing the return context that was in effect before event delivery.

22 . The apparatus of claim 21 , wherein the execution of the decoded instruction is to modify segment registers.

23 . The apparatus of claim 21 , wherein the opcode is F3 0F 01 CA.

24 . The apparatus of claim 21 , wherein the least privileged level is ring 3.

25 . The apparatus of claim 21 , wherein to execute the decode instruction the execution circuitry is to load and check the return context from a stack.

26 . The apparatus of claim 25 , wherein the execution circuitry is to check a shadow stack to confirm validity of the return.

27 . The apparatus of claim 25 , wherein the execution circuitry is to establish the return context by, at least in part, loading one or more registers.

28 . A method comprising:

decoding a single instruction, the single instruction to include a field for an opcode; and

executing the decoded instruction according to the opcode to cause a return from an event handler while transitioning to a least privileged ring and establishing the return context that was in effect before event delivery.

29 . The method of claim 28 , wherein executing the decoded instruction further comprises modifying segment registers.

30 . The method of claim 28 , wherein the opcode is F3 0F 01 CA.

31 . The method of claim 28 , wherein the least privileged level is ring 3.

32 . The method of claim 28 , wherein the executing further comprises loading and checking the return context from a stack.

33 . The method of claim 32 , wherein the executing is to check a shadow stack to confirm validity of the return.

34 . The method of claim 32 , wherein the executing is to establish the return context by, at least in part, loading one or more registers.

35 . A method comprising:

translating a single instruction from a first instruction set architecture into one or more instructions of a second instruction set architecture, the single instruction having a field for an opcode, the opcode indicating that execution circuitry is to cause a return from an event handler while transitioning to a least privileged level and establish a return context that was in effect before event delivery;

decoding the one or more instructions of the second instruction set architecture; and

executing the decoded one or more instructions of the second instruction set architecture to cause a return from an event handler while transitioning to a least privileged level and establish a return context that was in effect before event delivery.

36 . The method of claim 35 , wherein the opcode is F3 0F 01 CA.

37 . The method of claim 35 , wherein the least privileged level is ring 3.

38 . A system comprising:

a processor core including:

decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, and

execution circuitry to execute the decoded instruction according to the opcode to cause a return from an event handler while transitioning to a least privileged ring and establishing the return context that was in effect before event delivery; and

memory coupled to the processor core to store the single instruction.

39 . The system of claim 38 , wherein the opcode is F3 0F 01 CA.

40 . The system of claim 38 , wherein the execution circuitry is to establish the return context by, at least in part, loading one or more registers.

41 . An apparatus comprising:

event delivery circuitry to perform one or more operations upon an event delivery of an exception or interrupt to an event handler, wherein the one or more operations include an establishment of a new context of an event handler in a first privilege level; and

one or more model specific registers (MSRs) to be utilized by the event delivery circuitry to perform the one or more operations including one or more of:

a configuration MSR wherein a first proper subset of bits of the configuration register identify a stack level to use for markable interrupts that are delivered while current privilege level has a first state, a second proper subset of bits of the configuration register indicate the current privilege level state, a third proper subset of bits of the configuration register identify an amount of cachelines by which event delivery decrements a stack pointer when not changing stacks, and a fourth proper subset of bits of the configuration register contain the upper bits of the linear address of a page in memory containing event handlers;

a plurality of regular stack pointer MSRs;

a stack levels (STKLVLS) MSR; and

a plurality of shadow stack pointer MSRs.

42 . The apparatus of claim 41 , wherein the execution circuitry is to perform event delivery to:

determine a state of the new context;

save information about the event and an original context; and

load state of the new context.

43 . The apparatus of claim 41 , wherein to determine a state of the new context comprises to determine a new instruction pointer, a new flags register value, and values for a stack level, stack pointer, and a shadow stack pointer.

44 . The apparatus of claim 41 , wherein to save information about the event and an original context comprises to save information on a regular stack and to save information on a shadow stack.

45 . The apparatus of claim 41 , wherein the execution circuitry is to further confirm that the event delivery is supported by performing event delivery by determining that a bit in a control register is set to indicate support for flexible return and event delivery.

46 . The apparatus of claim 41 , further comprising:

memory to store the event handler.