High-speed broadside communications and control system
A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.
1. An integrated circuit comprising:
a communications input port configured to receive a packet that includes data;
a processor unit coupled to the communications input port, wherein the processor unit has an instruction set with a first bit width and the processor unit is coupled to the communications input port via an interface that has a second bit width that is greater than the first bit width;
a queue coupled to the processor unit; and
an application buffer coupled to the processor unit in parallel with the queue, wherein the processor unit is configured to:
receive the packet from the communications input port;
determine whether the data of the packet is real-time data or non-real-time data;
based on the data being real-time data, provide the data to the application buffer; and
based on the data being non-real-time data, provide the data to the queue.
2. The integrated circuit of claim 1 , wherein:
the processor unit is a first processor unit; and
the first processor unit is further configured to provide an interrupt to a second processor unit coupled to the first processor unit based on the data being real-time data.
3. The integrated circuit of claim 1 , wherein the second bit width is at least 1024 bits wide.
4. The integrated circuit of claim 1 , wherein the interface is configured to transfer at least 1024 bits per clock cycle of the processor unit.
5. The integrated circuit of claim 1 , wherein:
the packet is a first packet;
the communications input port is configured to receive a second packet;
the integrated circuit further comprises a communications output port coupled to the processor unit; and
the processor unit is configured to:
receive the second packet; and
forward the second packet to the communications output port.
6. The integrated circuit of claim 5 , wherein:
the processor unit is coupled to the communications output port via an interface that has the second bit width.
7. The integrated circuit of claim 1 , wherein the packet is an Ethernet packet.
8. A method comprising:
receiving a packet at a first processor unit via a communications input port, wherein:
the first processor unit has an instruction set with a first bit width;
the packet contains data;
the receiving of the packet at the first processor unit includes receiving the packet via an interface coupled between the first processor unit and the communications input port; and
the interface has a second bit width that is greater than the first bit width;
determine whether the data of the packet is associated with a real-time task or a non-real-time task;
determine whether to provide the data of the packet to a second processor unit via a queue or an application buffer based on whether the data of the packet is associated with the non-real-time task or the real-time task; and
provide the data to a determined one of the queue or the application buffer.
9. The method of claim 8 further comprising determining whether to provide an interrupt to the second processor unit based on whether the data of the packet is associated with the real-time task or the non-real-time task.
10. The method of claim 9 further comprising providing the interrupt to the second processor unit based on the data of the packet being associated with the real-time task.
11. The method of claim 8 , wherein the second bit width is at least 1024 bits wide.
12. The method of claim 8 , wherein the receiving of the packet via the interface includes receiving at least 1024 bits per clock cycle of the first processor unit.
13. The method of claim 8 , wherein:
the packet is a first packet; and
the method further comprises:
receiving a second packet at the first processor unit via the communications input port; and
forward the second packet to a communications output port.
14. The method of claim 13 , wherein:
the first processor unit has an instruction set with a first bit width;
the forwarding of the second packet is performed via an interface coupled between the first processor unit and the communications output port; and
the interface has a second bit width that is greater than the first bit width.
15. The method of claim 8 , wherein the packet is an Ethernet packet.
16. A system-on-a-chip comprising:
a communications input port configured to receive a packet that includes data;
a first processor unit that has a first bit width;
an interface coupled between the communications input port and the first processor unit, wherein the interface has a second bit width that is wider than the first processor unit;
a second processor unit;
a queue coupled between the first processor unit and the second processor unit;
an application buffer coupled between the first processor unit and the second processor unit, wherein the first processor unit is configured to:
receive the packet from the communications input port via the interface;
when the data is associated with a real-time task, provide the data to the second processor unit via the application buffer; and
when the data is associated with a non-real-time task, provide the data to the second processor unit via the queue.
17. The system-on-a-chip of claim 16 , wherein the first processor unit is configured to, when the data is associated with the real-time task, provide an interrupt to the second processor unit.
18. The system-on-a-chip of claim 16 , wherein the second bit width is at least 1024 bits in width.
19. The system-on-a-chip of claim 16 , wherein the interface is configured to transfer at least 1024 bits per clock cycle of the first processor unit.
20. The system-on-a-chip of claim 16 , wherein the communications input port is an Ethernet port.