Semiconductor memory device having a passivation film and a plurality of insulating patterns on a memory cell array
According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.
1. A semiconductor memory device comprising:
a memory cell array that includes a plurality of first interconnect layers and a first memory pillar, the first interconnect layers extending in a first direction substantially parallel to a semiconductor substrate, and the first memory pillar passing through the first interconnect layers and extending in a second direction substantially perpendicular to the semiconductor substrate;
a passivation film above the memory cell array;
a plurality of first insulating pattern layers above the passivation film, the first insulating pattern layers extending in the first direction and at least above the memory cell array, and arranged side by side in a third direction that is substantially parallel to the semiconductor substrate and intersects the first direction; and
a plurality of second insulating pattern layers above the passivation film, the second insulating pattern layers extending in the third direction and at least above the memory cell array, and arranged side by side in the first direction.
2. The semiconductor memory device according to claim 1 , wherein the first insulating pattern layers and the second insulating pattern layers have a compressive stress.
3. The semiconductor memory device according to claim 1 , further comprising a resin above the first insulating pattern layers and the second insulating pattern layers.
4. The semiconductor memory device according to claim 1 , wherein the first memory pillar includes a charge storage layer and a semiconductor layer.
5. The semiconductor memory device according to claim 1 , wherein the first insulating pattern layers and the second insulating pattern layers are silicon nitride having a compressive stress.
6. The semiconductor memory device according to claim 5 , further comprising:
an insulating layer provided between the passivation film and the first insulating pattern layers and between the passivation film and the second insulating pattern layers, and including silicon oxide.
7. The semiconductor memory device according to claim 1 , further comprising:
an etching stopper layer provided between the passivation film and the first insulating pattern layers and between the passivation film and the second insulating pattern layers.
8. The semiconductor memory device according to claim 1 , further comprising:
a first insulating layer provided between the first insulating pattern layers and arranged side by side in the third direction; and
a second insulating layer provided between the second insulating pattern layers and arranged side by side in the first direction,
wherein the first and second insulating layers include silicon oxide.