Common cooling solution for multiple packages

1. An apparatus comprising:

a first die package bonded to a first substrate;

a second die package bonded to a second substrate, the second substrate coupled to the first substrate; and

a cooling element thermally coupled to the first die package and the second die package by a planar surface of the cooling element, wherein only one side of each of the first die package and the second die package are coplanar and directly thermally coupled to the cooling element via a first portion of a thermal interface material and a second portion of the thermal interface material, respectively.

2. The apparatus of claim 1 , wherein the first die package comprises an application processing unit (APU) die package.

3. The apparatus of claim 1 , further comprising a discrete graphics processing unit (dGPU) comprising the second substrate and the second die package.

4. The apparatus of claim 1 , wherein

the first portion of the thermal interface material and the second portion of the thermal interface material are of a substantially same thickness.

5. The apparatus of claim 1 , wherein the first portion of the thermal interface material or the second portion of the thermal interface material comprises a thermal paste.

6. The apparatus of claim 1 , wherein the cooling element comprises a fluid-cooled cooling element.

7. The apparatus of claim 1 , wherein the planar surface of the cooling element comprises a surface of a layer of conductive metal.

8. A semiconductor chip device comprising:

a semiconductor chip substrate;

a first die package mounted on the semiconductor chip substrate, the first die package comprising an exposed surface; and

a second die package bonded on a second substrate and electrically coupled to the semiconductor chip substrate, the second substrate coupled to the semiconductor chip substrate, the second die package having an exposed surface at a same height as the first die package, wherein the exposed surface of the first die package and the second die package are configured to be thermally coupled to a cooling element, wherein only one side of each of the first die package and the second die package are coplanar and directly thermally coupled to the cooling element via a first portion of a thermal interface material and a second portion of the thermal interface material, respectively.

9. The apparatus of claim 1 , wherein the second die package is coupled to the first substrate via a peripheral interface.

10. The semiconductor chip device of claim 8 , wherein the first die package comprises an application processing unit (APU) die package.

11. The semiconductor chip device of claim 8 , further comprising a discrete graphics processing unit (dGPU) comprising the second substrate and the second die package.

12. The semiconductor chip device of claim 8 , wherein:

the first portion of the thermal interface material and the second portion of the thermal interface material are of a substantially same thickness.

13. The semiconductor chip device of claim 8 , wherein the first portion of thermal interface material or the second portion of thermal interface material comprises a thermal paste.

14. The semiconductor chip device of claim 8 , wherein the second die package is coupled to the semiconductor chip substrate via a peripheral interface.

15. A method for a common cooling solution for multiple packages, comprising:

thermally coupling a planar surface of a cooling element to a first die package bonded to a first substrate; and

thermally coupling the planar surface of the cooling element to a second die package bonded to a second substrate, wherein the second substrate is coupled to the first substrate, and only one side of each of the first die package and the second die package are coplanar and directly thermally coupled to the cooling element via a first portion of a thermal interface material and a second portion of the thermal interface material, respectively.

16. The method of claim 15 , wherein:

the first portion of thermal interface material and the second portion of thermal interface material are of a substantially same thickness.

17. The method of claim 15 , wherein the first die package comprises an application processing unit (APU) die package.

18. The method of claim 15 , wherein the second die package comprises a discrete graphics processing unit (dGPU) die package.

19. The method of claim 15 , wherein the cooling element comprises a fluid-cooled cooling element.

20. The method of claim 15 , wherein the planar surface of the cooling element comprises a surface of a layer of conductive metal.