Complementary envelope detector
A complementary envelope detector contemplates using two pair of mirrored transistors to provide a differential output envelope signal to an associated envelope tracking integrated circuit (ETIC) that supplies control voltages to an array of power amplifiers. While bipolar junction transistors (BJTs) may be used, other exemplary aspects use field effect transistors (FETs). In an exemplary aspect, a first pair are negative channel FETs (nFETs) and a second pair are positive channel FETs (pFETs).
1. An envelope detector circuit comprising:
an input comprising a positive input line and a negative input line;
a first transistor pair comprising:
a first transistor coupled to the positive input line;
a second transistor coupled to the negative input line; and
a first pair output;
a second transistor pair comprising:
a third transistor coupled to the positive input line;
a fourth transistor coupled to the negative input line; and
a second pair output;
an output comprising:
a positive output line coupled to the first pair output; and
a negative output line coupled to the first pair output and the second pair output; and
a filter comprising at least one resistor and one capacitor, the filter positioned within the negative output line between the first pair output and the second pair output.
2. The envelope detector circuit of claim 1 , wherein the transistors comprise field effect transistors (FETs).
3. The envelope detector circuit of claim 2 , wherein the first transistor and the second transistor comprise negative channel FETs (nFETs), each comprising a respective source, drain, and gate.
4. The envelope detector circuit of claim 3 , wherein the first pair output couples to the source of the first transistor and the source of the second transistor.
5. The envelope detector circuit of claim 3 , wherein the positive input line couples to the gate of the first transistor; and
the negative input line couples to the gate of the second transistor.
6. The envelope detector circuit of claim 3 , wherein the third transistor and the fourth transistor comprise positive channel FETs (pFETs), each comprising a respective source, drain, and gate.
7. The envelope detector circuit of claim 6 , wherein the positive input line couples to the gate of the third transistor; and
the negative input line couples to the gate of the fourth transistor.
8. The envelope detector circuit of claim 2 further comprising a feedback circuit coupling the negative output line to the input.
9. The envelope detector circuit of claim 3 , further comprising a supply voltage input coupled to the drains of the first and second FETs.
10. The envelope detector circuit of claim 1 , further comprising:
a second input;
a third transistor pair coupled to the first pair output and the second input; and
a fourth transistor pair coupled to the second pair output and the second input.
11. The envelope detector of claim 1 , wherein the transistors comprise bipolar junction transistors (BJTs).
12. The envelope detector of claim 11 , wherein the first and second transistors comprise npn BJTs and the third and fourth transistors comprise pnp BJTs, each transistor having a respective collector, base, and emitter.
13. The envelope detector of claim 12 , wherein the positive input line couples to the base of the first and third transistors and the negative input line couples to the base of the second and fourth transistors.
14. The envelope detector of claim 12 , wherein the positive output line couples to the first pair output and wherein the negative output line couples to the first pair output and the second pair output.
15. The envelope detector of claim 12 , wherein the first pair output comprises a node joining the emitters of the first and second transistors and the second pair output comprises a second node joining the emitters of the third and fourth transistors.
16. A wireless device comprising:
an envelope detector circuit comprising:
an input comprising a positive input line and a negative input line;
a first transistor pair comprising:
a first transistor coupled to the positive input line;
a second transistor coupled to the negative input line; and
a first pair output;
a second transistor pair comprising:
a third transistor coupled to the positive input line;
a fourth transistor coupled to the negative input line; and
a second pair output;
an output comprising:
a positive output line coupled to the first pair output; and
a negative output line coupled to the first pair output and the second pair output; and
a filter comprising at least one resistor and one capacitor, the filter positioned within the negative output line between the first pair output and the second pair output; and
an envelope tracking (ET) radio frequency (RF) front-end circuits comprising:
an ET integrated circuit (ETIC) coupled to the output, the ETIC configured to generate at least one control voltage based on a signal from the envelope detector circuit; and
a plurality of power amplifiers coupled to a plurality of antenna ports, respectively, at least one of the plurality of power amplifiers coupled to the ETIC and configured to receive the at least one control voltage.
17. The wireless device of claim 16 , wherein the transistors comprise field effect transistors (FETs).
18. The wireless device of claim 16 , wherein the transistors comprise bipolar junction transistors (BJTs).
19. The wireless device of claim 16 , further comprising a baseband circuit and an intermediate frequency (IF) circuit, wherein the envelope detector circuit is configured to detect an IF signal in the IF circuit.