Verification platform for system on chip and verification method thereof

1. A verification platform for a system on chip, comprising:

a bus function model unit connected to a bus, wherein the bus function model unit is provided with a storage area, a central processing unit accesses the storage area through the bus, and an Universal Verification Methodology test instance directly accesses the storage area;

wherein the Universal Verification Methodology test instance generates constrained random parameters and random controls and saves them to the storage area, and a software test instance reads the constrained random parameters and the random controls through the central processing unit and configures a test of the system on chip, and execution status information of the software test instance is stored in the storage area through the central processing unit and is read by the Universal Verification Methodology test instance.

2. The verification platform for the system on chip according to claim 1 , wherein the execution status information comprises information on whether the software test instance is executed successful, information on whether there is an error during execution and corresponding error information, a feedback from the tested system on chip during execution, execution coverage of the software code, or any combination thereof.

3. The verification platform for the system on chip according to claim 1 , wherein the system on chip comprises the central processing unit, a plurality of IP core modules and the bus, wherein each IP core module is connected to the bus respectively, and the central processing unit is connected to the bus.

4. The verification platform for the system on chip according to claim 3 , wherein the bus function model unit and an IP core module are connected to the bus through a selection switch, and interface protocols of the bus function model unit and the IP core module are the same and conform to an interface protocol of the bus.

5. The verification platform for the system on chip according to claim 1 , wherein the bus function model unit has an interface that conforms to the bus protocol and is directly connected to the bus.

6. The verification platform for the system on chip according to claim 1 , wherein the Universal Verification Methodology test instance reads the execution status information, adjusts constraint condition for generating random parameters and random controls based on the execution status information to exclude scenarios that have been tested, and converts the execution status information into coverage data for coverage analysis.

7. A verification method for a system on chip, comprising:

generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area in a bus function model unit;

reading, by a software test instance, the constrained random parameters and the random controls through a central processing unit, and configuring a test of the system on chip;

storing execution status information of the software test instance in the storage area; and

reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude scenarios that have been tested.

8. The verification method for the system on chip according to claim 7 , further comprising: converting the execution status information into coverage data for coverage analysis.