Microelectronic devices and electronic systems
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.
1. A microelectronic device, comprising:
array regions individually comprising:
memory cells comprising capacitors and access devices vertically overlying and in electrical communication with the capacitors;
digit lines operably associated with the memory cells and horizontally extending in a first direction;
word lines operably associated with the memory cells and horizontally extending in a second direction perpendicular to the first direction; and
CMOS circuitry vertically overlying and in electrical communication with the memory cells, the CMOS circuitry comprising:
transistors including gate electrodes vertically underlying channels; and
routing structures coupled to the transistors and vertically interposed between the transistors and the memory cells;
digit line exit regions horizontally alternating with rows of the array regions in the first direction and individually comprising:
portions of the digit lines horizontally extending beyond boundaries of the rows of the array regions horizontally adjacent thereto; and
digit line contact structures physically contacting and vertically extending completely through at least some of the portions of the digit lines, the digit line contact structures coupled to some of the routing structures;
word line exit regions horizontally alternating with columns of the array regions in the second direction and individually comprising:
portions of the word lines horizontally extending beyond boundaries of the columns of the array regions horizontally adjacent thereto; and
word line contact structures physically contacting and vertically extending completely through at least some of the portions of the word lines, the word line contact structures coupled to some other of the routing structures.
2. The microelectronic device of claim 1 , further comprising socket regions horizontally offset from the array regions, the digit line exit regions, and the word line exit regions, the socket regions individually comprising additional CMOS circuitry vertically overlying the memory cells of the array regions and having different configurations and operational functions than the CMOS circuitry.
3. The microelectronic device of claim 1 , wherein the CMOS circuitry within each array region of the array regions comprise:
sense amplifier circuits within two sense amplifier regions positioned proximate corners of the array region diagonally opposing one another; and
sub-word line driver circuits within two sub-word line driver regions positioned proximate additional corners of the array region diagonally opposing one another.
4. The microelectronic device of claim 3 , wherein, for each sense amplifier region of the two sense amplifier regions within the array region:
some of the sense amplifier circuits within the sense amplifier region are coupled to some of the digit lines horizontally extending through the array region; and
some other of the sense amplifier circuits within the sense amplifier region are coupled to some of the digit lines horizontally extending through an additional one of the array regions horizontally neighboring the array region.
5. The microelectronic device of claim 4 , wherein:
the some of the sense amplifier circuits are coupled to the some of the digit lines horizontally extending through the array region by way of some of the digit line contact structures and a group of the some of the routing structures within one of the digit line exit regions horizontally interposed between the array region and the additional one of the array regions; and
the some other of the sense amplifier circuits are coupled to the some of the digit lines horizontally extending through the additional one of the array regions by way of some other of the digit line contact structures and an additional group of the some of the routing structures within the one of the digit line exit regions.
6. The microelectronic device of claim 3 , wherein, for each sub-word line driver region of the two sub-word line driver regions within the array region:
some of the sub-word line driver circuits within the sub-word line driver region are coupled to some of the word lines horizontally extending through the array region; and
some other of the sub-word line driver circuits within the sub-word line driver region are coupled to some of the word lines horizontally extending through an additional one of the array regions horizontally neighboring the array region.
7. The microelectronic device of claim 6 , wherein:
the some of the sub-word line driver circuits is coupled to the some of the word lines horizontally extending through the array region by way of some of the word line contact structures and a group of the some other of the routing structures within one of the word line exit regions horizontally interposed between the array region and the additional one of the array regions; and
the some other of the sub-word line driver circuits is coupled to the some of the word lines horizontally extending through the additional one of the array regions by way of some other of the word line contact structures and an additional group of the some other of the routing structures within the one of the word line exit regions.
8. The microelectronic device of claim 1 , further comprising:
further routing structures vertically overlying the CMOS circuitry and in electrical communication with the memory cells of the array regions; and
conductive pad structures vertically overlying and in electrical communication with the further routing structures.
9. An electronic system, comprising:
an input device;
an output device;
a processor device operably connected to the input device and the output device; and
a memory device operably connected to the processor device and comprising:
memory array regions each comprising:
dynamic random access memory (DRAM) cells;
digit lines coupled to the DRAM cells;
word lines coupled to the DRAM cells; and
CMOS circuitry overlying and in electrical communication with the DRAM cells, the CMOS circuitry comprising:
transistors including gate structures vertically underlying channel structures; and
routing structures coupled to the transistors and vertically interposed between the transistors and the DRAM cells;
a digit line contact region horizontally interposed between two of the memory array regions horizontally neighboring one another in a first direction, the digit line contact region comprising:
end portions of some of the digit lines extending past horizontal boundaries of the two of the memory array regions; and
digit line contacts coupled to and extending completely through the end portions of the some of the digit lines, the digit line contacts coupled to some of the routing structures;
a word line contact region horizontally interposed between two other of the memory array regions horizontally neighboring one another in a second direction perpendicular to the first direction, the word line contact region comprising:
end portions of some of the word lines extending past horizontal boundaries of the two other of the memory array regions; and
word line contacts coupled to and extending completely through the end portions of the some of the word lines, the word line contacts coupled to some other of the routing structures.