Transistor structure

1. A transistor structure, comprising:

a source region and a drain region disposed in a substrate and extend along a first direction;

a polysilicon layer disposed over the substrate and extending along a second direction perpendicular to the first direction, wherein

the polysilicon layer comprises a first edge region, a second edge region, and a channel region between the first edge region and the second edge region, and

the first edge region, the channel region and the second edge region are formed as a gate region between the source region and the drain region in a plane view; and

a gate insulation layer disposed between the polysilicon layer and the substrate, wherein

the transistor structure comprises a first edge transistor, a main channel transistor, and a second edge transistor,

a thickness of the gate insulation layer in the main channel transistor is greater than a thickness of the gate insulation layer in the first edge transistor and a thickness of the gate insulation layer in the second edge transistor,

the first edge transistor, the main channel transistor, and the second edge transistor respectively correspond to the first edge region, the channel region, and the second edge region,

the polysilicon layer comprises a first opening pattern at the first edge region and a second opening pattern at the second edge region, the first opening pattern has a first portion overlapping with the gate region, the second opening pattern has a second portion overlapping with the gate region, and

the transistor structure further comprises:

a first isolation structure connected to a first side of the gate insulation layer; and

a second isolation structure connected to a second side of the gate insulation layer, wherein

the first side and the second side are opposite sides of the gate insulation layer,

the polysilicon layer is located on the gate insulation layer, the first isolation structure, and the second isolation structure, and

the substrate has a channel under the gate insulation layer and between the source region and the drain region in the plane view.

2. The transistor structure according to claim 1 , wherein

the first opening pattern partially exposes the gate insulation layer directly above the channel and partially exposes the first isolation structure, and

the second opening pattern partially exposes the gate insulation layer directly above the channel and partially exposes the second isolation structure.

3. The transistor structure according to claim 2 , wherein

the first opening pattern partially exposes the gate insulation layer directly above at least one of the source region and the drain region, and

the second opening pattern partially exposes the gate insulation layer directly above at least one of the source region and the drain region.

4. The transistor structure according to claim 2 , wherein

the first opening pattern partially exposes the gate insulation layer directly above at least one of the source region and the drain region, and

the second opening pattern does not expose the gate insulation layer directly above the source region and the gate insulation layer directly above the drain region.

5. The transistor structure according to claim 2 , wherein

the first opening pattern does not expose the gate insulation layer directly above the source region and the gate insulation layer directly above the drain region, and

the second opening pattern does not expose the gate insulation layer directly above the source region and the gate insulation layer directly above the drain region.

6. The transistor structure according to claim 1 , further comprising a first lightly doped region and a second lightly doped region in the substrate, wherein the first lightly doped region and the second lightly doped region are located on two sides of the polysilicon layer in the plane view corresponding to the source region and the drain region.

7. The transistor structure according to claim 6 , wherein the first opening pattern partially exposes the gate insulation layer directly above at least one of the first lightly doped region and the second lightly doped region.

8. The transistor structure according to claim 7 , wherein the second opening pattern partially exposes the gate insulation layer directly above at least one of the first lightly doped region and the second lightly doped region.

9. The transistor structure according to claim 6 , wherein a part of the lightly doped region overlaps with the polysilicon layer.

10. The transistor structure according to claim 6 , wherein a part of the lightly doped region does not overlap with the polysilicon layer.

11. The transistor structure according to claim 1 , wherein at least one of the first opening pattern and the second opening pattern is disposed over the source region and the drain region.

12. The transistor structure according to claim 1 , wherein at least one of the first opening pattern and the second opening pattern comprises an opening located between the source region and the drain region without overlapping the source region and the drain region.

13. The transistor structure according to claim 1 , wherein

the first opening pattern includes a first opening and a second opening,

the first opening is disposed over the source region,

the second opening is disposes over the drain region,

the second opening pattern includes a third opening and a fourth opening,

the third opening is disposed over the source region, and

the fourth opening is disposed over the drain region.

14. The transistor structure according to claim 1 , wherein the first opening pattern and the second opening pattern are not distributed into the channel region.

15. The transistor structure according to claim 1 , wherein the first opening pattern is different from the second opening pattern in opening distribution.

16. The transistor structure according to claim 1 , wherein each of the first opening pattern and the second opening pattern has a single opening.

17. The transistor structure according to claim 1 , wherein

the gate insulation layer at the first edge region corresponds to the first edge transistor, and

the gate insulation layer at the second edge region corresponds to the second edge transistor.