Semiconductor package
A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.
1. A semiconductor package comprising:
an interposer substrate;
first to third semiconductor chips on the interposer substrate to face each other;
an underfill part between each of the first to third semiconductor chips and the interposer substrate;
a first side-fill part extending upward from lower ends of side walls of the first to third semiconductor chips; and
a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to upper ends of the side walls of the first to third semiconductor chips,
wherein an upper surface of the first semiconductor chip comprises a first edge facing the second semiconductor chip, a second edge facing the third semiconductor chip, and a first corner at which the first edge meets the second edge,
an upper surface of the second semiconductor chip comprises a third edge facing the first semiconductor chip, a fourth edge facing the third semiconductor chip, and a second corner at which the third edge meets the fourth edge,
the second side-fill part extends from the first corner of the first semiconductor chip along each of the first edge and the second edge of the first semiconductor chip and extends from the second corner of the second semiconductor chip along each of the third edge and the fourth edge of the second semiconductor chip, and
a coefficient of thermal expansion of the second side-fill part is less than a coefficient of thermal expansion of the first side-fill part.
2. The semiconductor package of claim 1 , wherein the second side-fill part is in contact with a portion of the first edge and a portion of the second edge of the first semiconductor chip and a portion of the third edge and a portion of the fourth edge of the second semiconductor chip.
3. The semiconductor package of claim 2 , wherein the first side-fill part is in contact with a remaining portion of the first edge and a remaining portion of the second edge of the first semiconductor chip and a remaining portion of the third edge and a remaining portion of the fourth edge of the second semiconductor chip.
4. The semiconductor package of claim 1 , wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are apart from each other at a distance of about 20 μm to about 200 μm.
5. The semiconductor package of claim 1 , wherein first content of a filler contained in the second side-fill part is greater than second content of a filler contained in the first side-fill part.
6. The semiconductor package of claim 1 , wherein a particle size of a filler contained in the second side-fill part is greater than a particle size of a filler contained in the first side-fill part.
7. The semiconductor package of claim 1 , further comprising:
a molding part on the interposer substrate to mold the first to third semiconductor chips, the molding part including a same material as the second side-fill part;
a package substrate under the interposer substrate; and
an insulating filler material filling between the package substrate and the interposer substrate and covering a portion of a side wall of the molding part and a side wall of the interposer substrate.
8. The semiconductor package of claim 7 , further comprising:
a heat-dissipating member on the first to third semiconductor chips; and
a thermal interface material between the first to third semiconductor chips and the heat-dissipating member.
9. The semiconductor package of claim 1 , wherein the interposer substrate comprises:
a base layer including silicon;
a redistribution structure arranged on the base layer and comprising a conductive redistribution pattern; and
a through electrode passing through the base layer and electrically connected to the conductive redistribution pattern.
10. A semiconductor package comprising:
a base;
at least three semiconductor chips on the base to face each other, the at least three semiconductor chips electrically connected to the base, the at least three semiconductor chips comprising a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip;
an underfill part between the at least three semiconductor chips and the base;
a first side-fill part extending upward from lower ends of side walls of the at least three semiconductor chips; and
a second side-fill part between the side walls of the at least three semiconductor chips and extending from the first side-fill part to upper ends of the side walls of the at least three semiconductor chips,
wherein the second side-fill part is in contact with each of the at least three semiconductor chips,
first content of a filler contained in the second side-fill part is greater than second content of a filler contained in the first side-fill part,
when viewed in a plan view, the second side-fill part is surrounded by the first side-fill part and is at a position at which the at least three semiconductor chips adjoin each other, and
when viewed in a plan view, the second side-fill part comprises a first portion between the first semiconductor chip and the second semiconductor chip, a second portion between the second semiconductor chip and the third semiconductor chip, and a third portion between the first semiconductor chip and the third semiconductor chip, the first to third portions of the second side-fill part connected to each other as a unitary mass.
11. The semiconductor package of claim 10 , wherein the base comprises a semiconductor chip or an interposer substrate.
12. The semiconductor package of claim 10 , wherein
an upper surface of the first semiconductor chip comprises a first edge facing the second semiconductor chip, a second edge facing the third semiconductor chip, and a first corner at which the first edge meets the second edge, and
the second side-fill part extends from the first corner of the first semiconductor chip along each of the first edge and the second edge of the first semiconductor chip.
13. The semiconductor package of claim 12 , wherein
the second side-fill part is in contact with a portion of the first edge and a portion of the second edge of the first semiconductor chip, and
the first side-fill part is in contact with a remaining portion of the first edge and a remaining portion of the second edge of the first semiconductor chip.
14. The semiconductor package of claim 13 , wherein
an upper surface of the second semiconductor chip comprises a third edge facing the first semiconductor chip, a fourth edge facing the third semiconductor chip, and a second corner at which the third edge meets the fourth edge,
the second side-fill part extends from the second corner of the second semiconductor chip along each of the third edge and the fourth edge of the second semiconductor chip,
the second side-fill part is in contact with a portion of the third edge and a portion of the fourth edge of the second semiconductor chip, and
the first side-fill part is in contact with the other portion of the third edge and the other portion of the fourth edge of the second semiconductor chip.
15. The semiconductor package of claim 10 , wherein
the at least three semiconductor chips comprise four semiconductor chips arranged in a quadrangular form, and
the second side-fill part is in contact with each of the four semiconductor chips and has a cross shape in a plan view.
16. The semiconductor package of claim 10 , wherein upper surfaces of the at least three semiconductor chips are coplanar with an upper surface of the first side-fill part and an upper surface of the second side-fill part.
17. The semiconductor package of claim 10 , further comprising:
a molding part on the base, the molding part molding the at least three semiconductor chips and including a same material as the second side-fill part.
18. The semiconductor package of claim 17 , wherein the molding part covers upper surfaces of the at least three semiconductor chips and is connected to the second side-fill part.
19. A semiconductor package comprising:
an interposer substrate;
a plurality of semiconductor chips on the interposer substrate, each of the plurality of semiconductor chips comprising a lower surface facing the interposer substrate and an upper surface that is opposite to the lower surface, the plurality of semiconductor chips comprising a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip;
a first side-fill part filling between side walls of the plurality of semiconductor chips and extending upward from lower ends of the side walls of the plurality of semiconductor chips; and
a second side-fill part between the side walls of the plurality of semiconductor chips and extending downward from upper ends of the side walls of the plurality of semiconductor chips,
wherein the second side-fill part is in contact with an upper portion of at least one of side walls of each of the plurality of semiconductor chips,
the first side-fill part is in contact with a remaining portion of the at least one of the side walls of each of the plurality of semiconductor chips, and
a particle size of a filler contained in the second side-fill part is greater than a particle size of a filler contained in the first side-fill part, and
when viewed in a plan view, the second side-fill part is surrounded by the first side-fill part and is at a position at which the plurality of semiconductor chips adjoin each other, and
when viewed in a plan view, the second side-fill part comprises a first portion between the first semiconductor chip and the second semiconductor chip, a second portion between the second semiconductor chip and the third semiconductor chip, and a third portion between the first semiconductor chip and the third semiconductor chip, the first to third portions of the second side-fill part connected to each other as a unitary mass.