Semiconductor devices and electronic systems including the same

1. A semiconductor device comprising:

gate stacks on a substrate and spaced apart from each other in a first direction parallel to an upper surface of the substrate, the gate stacks comprising electrodes and cell insulating layers that are alternately stacked, the substrate comprising a cell array region and a connection region adjacent to the cell array region in a second direction parallel to the upper surface of the substrate and crossing the first direction;

a separation structure between the gate stacks and extending in the second direction;

vertical structures penetrating the gate stacks and having vertical semiconductor patterns extending in a third direction perpendicular to the upper surface of the substrate and conductive pads directly connected to upper surfaces of the vertical semiconductor patterns;

a supporting structure on the gate stacks, the supporting structure extending from the cell array region into the connection region;

bit lines on the supporting structure; and

contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures, the contact plugs directly connected to upper surfaces of the conductive pads,

wherein a bottom surface of a portion of the supporting structure on an upper surface of the separation structure is lower than top surfaces of the conductive pads.

2. The semiconductor device of claim 1 ,

wherein the bottom surface of the portion of the supporting structure on the separation structure is on a top surface of the separation structure and is higher than bottom surfaces of the conductive pads, and

wherein a top surface of the portion of the supporting structure on the separation structure is higher than the top surfaces of the conductive pads.

3. The semiconductor device of claim 1 , wherein a thickness of the supporting structure is about 4 to about 6 times a thickness of the conductive pads.

4. The semiconductor device of claim 1 , wherein the supporting structure comprises a material whose hardness is greater than the cell insulating layers of the gate stacks.

5. The semiconductor device of claim 1 ,

wherein the supporting structure comprises a plurality of openings along the separation structure, and

wherein the separation structure extends into the openings.

6. The semiconductor device of claim 5 ,

wherein the separation structure comprises:

first portions that extend into the openings; and

second portions that are between the openings,

wherein top surfaces of the second portions are lower than the top surfaces of the conductive pads, and

wherein top surfaces of the first portions are higher than the top surfaces of the conductive pads.

7. The semiconductor device of claim 6 , further comprising an interface insulating layer between the vertical structures and the electrodes,

wherein the interface insulating layer extends to a region on the second portions of the separation structure, and

wherein the interface insulating layer is in contact with the bottom surface of the portion of the supporting structure on the separation structure.

8. The semiconductor device of claim 5 ,

wherein the separation structure comprises a first separation structure and a second separation structure that are adjacent to each other in the first direction,

wherein the openings comprise first openings on the first separation structure and second openings on the second separation structure, and

wherein the second openings are shifted from the first openings in the second direction.

9. The semiconductor device of claim 5 ,

wherein the substrate comprises a cell array region and a connection region,

wherein the supporting structure is on the cell array region and the connection region, and

wherein the openings are on the cell array region and the connection region.

10. The semiconductor device of claim 9 , wherein first ones of the openings on the connection region are longer in the second direction than second ones of the openings on the cell array region.

11. The semiconductor device of claim 9 ,

wherein the separation structure comprises:

a first separation structure that extends from the cell array region to the connection region; and

second separation structures that are offset from the first separation structure in the first direction,

wherein the second separation structures penetrate the gate stacks and are spaced apart from each other in the second direction, in the connection region, and

wherein the openings on the connection region overlap the second separation structures.

12. The semiconductor device of claim 5 ,

wherein the portion of the supporting structure on the separation structure comprises a first bridge portion among a plurality of bridge portions that are on the separation structure and between the openings, and

wherein the plurality of bridge portions are between the gate stacks.

13. The semiconductor device of claim 1 , wherein the bottom surface of the portion of the supporting structure on the separation structure is lower than bottom surfaces of the contact plugs.

14. The semiconductor device of claim 1 ,

wherein the supporting structure comprises a first supporting layer and a second supporting layer on the first supporting layer,

wherein a top surface of the first supporting layer is substantially coplanar with the top surfaces of the conductive pads, and

wherein a top surface of the second supporting layer is substantially coplanar with top surfaces of the contact plugs.

15. A semiconductor device comprising:

a peripheral circuit structure; and

a cell array structure on the peripheral circuit structure,

wherein the cell array structure comprises:

a lower semiconductor layer and a source semiconductor layer on the lower semiconductor layer;

gate stacks on the source semiconductor layer and spaced apart from each other in a first direction parallel to an upper surface of the substrate, the gate stacks including electrodes and cell insulating layers, alternately stacked in a third direction perpendicular to the upper surface of the substrate;

a separation structure between the gate stacks and extending in a second direction parallel to the upper surface of the substrate and crossing the first direction;

vertical structures that penetrate the gate stacks in the third direction and are electrically connected to the source semiconductor layer, the vertical structures having conductive pads on upper portions thereof;

an interface insulating layer between the vertical structures and the electrodes;

a supporting structure on the gate stacks;

bit lines on the supporting structure; and

contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures,

wherein the supporting structure comprises a plurality of openings arranged in the second direction along the separation structure, the plurality of openings at least partially overlapping portions of the separation structure when viewed in a plan view,

wherein the separation structure comprises first portions that extend into the openings and second portions that are between the openings, and

wherein a top surface of a portion of the interface insulating layer that extends into a region between the second portions of the separation structure and the supporting structure is lower than top surfaces of the conductive pads.

16. The semiconductor device of claim 15 ,

wherein the supporting structure further comprises bridge portions that are on the separation structure and between the openings, and

wherein the bridge portions are between the gate stacks.

17. The semiconductor device of claim 15 , wherein a bottom surface of the supporting structure is higher than bottom surfaces of the conductive pads.

18. The semiconductor device of claim 15 , wherein top surfaces of the first portions are higher than the top surfaces of the conductive pads.

19. An electronic system comprising:

a main substrate;

a semiconductor device on the main substrate, and

a controller on the main substrate and electrically connected to the semiconductor device,

wherein the semiconductor device comprises:

gate stacks that are spaced apart from each other in a first direction parallel to an upper surface of the main substrate, the gate stacks comprising electrodes and cell insulating layers that are alternately stacked in a third direction perpendicular to the upper surface of the main substrate;

a separation structure between the gate stacks and extending in a second direction parallel to the upper surface of the main substrate and crossing the first direction;

vertical structures penetrating the gate stacks and having vertical semiconductor patterns extending in the third direction and conductive pads directly connected to upper surfaces of the vertical semiconductor patterns;

a supporting structure on the gate stacks;

bit lines on the supporting structure;

contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures, the contact plugs directly connected to upper surfaces of the conductive pads;

a peripheral circuit electrically connected to the bit lines; and

an input/output pad electrically connected to the peripheral circuit,

wherein a bottom surface of a portion of the supporting structure on an upper surface of the separation structure is lower than top surfaces of the conductive pads and is higher than bottom surfaces of the conductive pads, with respect to the upper surface of the main substrate.

20. The electronic system of claim 19 ,

wherein the main substrate further comprises interconnection patterns electrically connecting the semiconductor device to the controller,

wherein the supporting structure comprises a plurality of openings along the separation structure,

wherein the separation structure comprises first portions that extend into the openings and second portions that are between the openings,

wherein the semiconductor device further comprises an interface insulating layer between the vertical structures and the electrodes, and

wherein a top surface of a portion of the interface insulating layer that extends into a region between the second portions of the separation structure and the supporting structure is lower than the top surfaces of the conductive pads.