Memory system
According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.
1. A method of controlling a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, the method comprising:
in response to a first command, applying a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell; and
in response to a second command, applying a fourth voltage to the first word line, applying a fifth voltage to the second word line, and applying a sixth voltage to the third word line, wherein
the first memory cell is turned on by the applying the fourth voltage regardless of data stored in the first memory cell,
the second memory cell is turned on by the applying the second voltage regardless of data stored in the second memory cell,
the second memory cell is turned on by the applying the fifth voltage regardless of data stored in the second memory cell,
the third memory cell is turned on by the applying the third voltage regardless of data stored in the third memory cell, and the
third memory cell is turned on by the applying the sixth voltage regardless of data stored in the third memory cell.
2. The method according to claim 1 , wherein the applying the fourth voltage, the fifth voltage and the sixth voltage is performed after the applying the first voltage and before data writing or data erasing is performed on one of the memory cells.
3. The method according to claim 1 , further comprising, in response to the first command, sending the first data.
4. The method according to claim 3 , wherein the method does not comprising, in response to the second command, sending data stored in one of the memory cells.
5. The method according to claim 1 , further comprising: performing error detection and error correction processes on the first data; and
copying data stored in a block including the first word line to the other block when the error detection and error correction processes on the first data are successful and a first shift amount from a value of a seventh voltage to a value of the first voltage is larger than a first value, the block being a data erasing unit.
6. The method according to claim 5 , further comprising:
reading data from the first memory cell as second data using eighth voltage when the error detection and error correction processes on the first data fail, the eighth voltage being different from the first voltage; and
performing error detection and error correction processes on the second data, and receiving the second command when the error detection and error correction processes on the second data are successful and a second shift amount from the value of the seventh voltage to a value of the eighth voltage is larger than the second value.
7. The method according to claim 6 , further comprising using the eighth voltage to read data stored in the first memory cell after receiving the second command.
8. The method according to claim 7 , further comprising managing information on a voltage to be applied to the first word line and updating the information to information corresponding to the eighth voltage.
9. The method according to claim 1 , wherein the first command is based on a read instruction from a host apparatus.
10. The method according to claim 1 , wherein the fourth voltage, the fifth voltage and the sixth voltage are equal to or larger than the third voltage.
11. The method according to claim 10 , wherein the fourth voltage, the fifth voltage and the sixth voltage have a same voltage value.
12. The method according to claim 3 , wherein the semiconductor memory device includes a second select transistor and a second select gate line, the second select transistor being connected in series with the memory cells, the second select gate line being electrically connected to a gate of the second select transistor, the method further comprising
in response to the second command, applying a ninth voltage to a fourth word line of the word lines and applying a tenth voltage to a fifth word line of the word lines after sending the first data, the fourth word line being electrically connected to a gate of a fourth memory cell of the memory cells connected in series with the first select transistor, the fifth word line being electrically connected to a gate of a fifth memory cell of the memory cells connected in series with the second select transistor.
13. The method according to claim 12 , wherein
the fourth memory cell is turned on by the applying the ninth voltage regardless of data stored in the fourth memory cell, and
the fifth memory cell is turned on by the applying the tenth voltage regardless of data stored in the fifth memory cell.
14. The method according to claim 13 , wherein the ninth voltage and the tenth voltage have a same voltage value.
15. The method according to claim 14 , wherein one of the fourth voltage, the fifth voltage and the sixth voltage is larger than one of the ninth voltage and the tenth.
16. The method according to claim 1 , wherein the second voltage is larger than the third voltage.
17. The method according to claim 1 , wherein a period in which the fourth voltage is applied to the first word line, a period in which the fifth voltage is applied to the second word line, and a period in which the sixth voltage is applied to the third word line are equal to or longer than a period in which the third voltage is applied to the third word line.
18. The method according to claim 1 , further receiving a fourth command before the second command for notifying at least one of a period in which the fourth voltage is applied to the first word line, a period in which the fifth voltage is applied to the second word line, and a period in which the sixth voltage is applied to the third word line.
19. The method according to claim 1 , wherein each of the plurality of memory cells is configured to store n-bit data (n is a natural number not less than 2).