Memory devices and methods of forming the same
A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
1. A memory device, comprising:
a first conductive plug disposed on a conductive line over a substrate;
a phase change layer disposed over the first conductive plug;
a buffer layer disposed between the first conductive plug and the phase change layer;
a filamentary bottom electrode disposed within the buffer layer and in physical contact with the first conductive plug and the phase change layer;
a top electrode disposed over the phase change layer; and
a second conductive plug disposed over the top electrode,
wherein a central axis of the phase change layer is misaligned with a central axis of the buffer layer.
2. The memory device of claim 1 , wherein the buffer layer has a flat top surface and a stepped bottom surface.
3. The memory device of claim 1 , further comprising a dielectric cap layer aside the buffer layer.
4. The memory device of claim 1 , wherein the buffer layer covers a top surface of the first conductive plug.
5. The memory device of claim 4 , wherein the buffer layer further covers a portion of a side surface of the first conductive plug.
6. The memory device of claim 5 , wherein the filamentary bottom electrode is in physical contact with a corner connecting the top surface and the portion of the side surface of the first conductive plug.
7. The memory device of claim 1 , wherein the buffer layer comprises metal oxide.
8. A memory device, comprising:
a first conductive line disposed over a substrate and extending in a first direction;
a phase change layer disposed over the first conductive line;
a selector layer disposed over the phase change layer;
a second conductive line disposed over the selector layer and extending in a second direction different from the first direction;
a buffer layer disposed between the first conductive line and the phase change layer;
a filament bottom electrode present within the buffer layer; and
a top electrode is disposed between the selector layer and the second conductive line,
wherein a central axis of the phase change layer is misaligned with a central axis of the buffer layer.
9. The memory device of claim 8 , wherein the filament bottom electrode comprises oxygen vacancies.
10. The memory device of claim 8 , wherein the buffer layer comprises metal oxide.
11. The memory device of claim 8 , wherein the phase change layer partially covers the buffer layer.
12. The memory device of claim 8 , further comprising a dielectric cap layer aside the buffer layer.
13. A memory device, comprising:
a first conductive plug disposed on a conductive line over a substrate;
a phase change layer disposed over the first conductive plug;
a buffer layer disposed between the first conductive plug and the phase change layer;
a filamentary bottom electrode disposed within the buffer layer and in physical contact with the first conductive plug and the phase change layer;
a top electrode disposed over the phase change layer; and
a second conductive plug disposed over the top electrode,
wherein the filament bottom electrode comprises oxygen vacancies, and
wherein a central axis of the phase change layer is misaligned with a central axis of the buffer layer.
14. The memory device of claim 13 , wherein the buffer layer comprises metal oxide.
15. The memory device of claim 13 , wherein the phase change layer partially covers the buffer layer.
16. The memory device of claim 13 , wherein the buffer layer covers a top surface of the first conductive plug.
17. The memory device of claim 16 , wherein the buffer layer further covers a portion of a side surface of the first conductive plug.
18. The memory device of claim 17 , wherein the filamentary bottom electrode is in physical contact with a corner connecting the top surface and the portion of the side surface of the first conductive plug.
19. The memory device of claim 13 , wherein the buffer layer has a flat top surface and a stepped bottom surface.
20. The memory device of claim 19 , further comprising a dielectric cap layer aside the buffer layer, and a bottom surface of the dielectric cap layer is substantially flushed with a lowermost bottom surface of the buffer layer.