Memory tiering techniques in computing systems

1. A method of memory management in a computing device having a processor, a first memory proximate to and configured as a cache for the processor, a second memory separate from and interfaced with the processor, and a memory controller configured to manage operations of the first and second memory, the method comprising:

receiving, at the memory controller, a request from the processor to read data corresponding to a system memory section from the cache of the processor; and

in response to receiving the request to read, with the memory controller,

retrieving, from a first section in the first memory, data from a data portion and metadata from a metadata portion in the first section of the first memory, the metadata from the metadata portion encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in the second memory;

analyzing the data location information in the retrieved metadata from the metadata portion of the first section in the first memory to determine whether the first section in the first memory currently contains data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first section in the first memory to the processor in response to the received request.

2. The method of claim 1 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received request; and

retrieving the data from the second section in the first memory or the memory location in the second memory and providing the retrieved data to the processor in response to the received request.

3. The method of claim 1 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request; and

writing, to the first section in the first memory, the retrieved data from the second section in the first memory.

4. The method of claim 1 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and

modifying the metadata in the metadata portion of the first memory to indicate that the data corresponding to the system memory section in the received request is now in the first section of the first memory.

5. The method of claim 1 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and

writing, to the second section in the first memory, the retrieved data from the first section of the first memory.

6. The method of claim 1 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received request,

retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request;

writing, to the first section in the first memory, the retrieved data from the second section in the first memory;

writing, to the second section in the first memory, the retrieved data from the first section of the first memory; and

modifying the metadata in the metadata portion in the first section of the first memory to indicate that:

the data corresponding to the system memory section in the received request is now in the first section of the first memory; and

the data previously held in the first section of the first memory is now in the second section of the first memory.

7. The method of claim 1 wherein:

the metadata from the metadata portion includes one or more bits; and

the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more bits; and

determining whether the identified combination corresponds to the system memory section in the received request.

8. The method of claim 1 wherein:

the metadata from the metadata portion includes one or more Error Checking and Correction (ECC) bits; and

the data location information includes combinations of the one or more ECC bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more ECC bits; and

determining whether the identified combination of ECC bits corresponds to the system memory section in the received request.

9. A computing device, comprising:

a processor;

a first memory proximate to and configured as a cache for the processor;

a second memory separate from and interfaced with the processor; and

a memory controller configured to manage operations of the first and second memory, wherein the memory controller having instructions executable by the memory controller to:

upon receiving a request from the processor to read data corresponding to a system memory section from the cache of the processor,

retrieve, from a first section of the first memory, data from a data portion and metadata from a metadata portion of the first section of the first memory, the metadata from the metadata portion encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections of the second memory;

analyze the data location information in the retrieved metadata from the metadata portion of the first section in the first memory to determine whether the first section in the first memory currently contains data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request, transmit the retrieved data from the data portion of the first section in the first memory to the processor in response to the received request.

10. The computing device of claim 9 wherein the memory controller includes additional instructions executable to:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyze the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received request; and

retrieve the data from the second section in the first memory or the memory location in the second memory and providing the retrieved data to the processor in response to the received request.

11. The computing device of claim 9 wherein the memory controller includes additional instructions executable to:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyze the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received request,

retrieve the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request; and

write, to the first section in the first memory, the retrieved data from the second section in the first memory.

12. The computing device of claim 9 wherein the memory controller includes additional instructions executable to:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyze the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

write, to the first section in the first memory, the retrieved data from the second section in the first memory; and

modify the metadata in the metadata portion of the first memory to indicate that the data corresponding to the system memory section in the received request is now in the first section of the first memory.

13. The computing device of claim 9 wherein the memory controller includes additional instructions executable to:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyze the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

retrieve the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request;

write, to the first section in the first memory, the retrieved data from the second section in the first memory; and

write, to the second section in the first memory, the retrieved data from the first section of the first memory.

14. The computing device of claim 9 wherein the memory controller includes additional instructions executable to:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyze the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request;

upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received request,

retrieve the data from the second section in the first memory and providing the retrieved data to the processor in response to the received request;

write, to the first section in the first memory, the retrieved data from the second section in the first memory;

write, to the second section in the first memory, the retrieved data from the first section of the first memory; and

modify the metadata in the metadata portion in the first section of the first memory to indicate that the data corresponding to the system memory section in the received request is now in the first section of the first memory and the data previously held in the first section of the first memory is now in the second section of the first memory.

15. The computing device of claim 9 wherein:

the metadata from the metadata portion includes one or more bits; and

the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and

to analyze the data location information includes:

identify a combination of the one or more bits; and

determine whether the identified combination corresponds to the system memory section in the received request.

16. A method of memory management in a computing device having a processor, a first memory proximate to and configured as a cache for the processor, a second memory separate from and interfaced with the processor, and a memory controller configured to manage operations of the first and second memory, the method comprising:

receiving, at the memory controller, a request from the processor to write a block of data corresponding to a system memory section to the cache of the processor; and

in response to receiving the request to write the block of data, with the memory controller,

retrieving, from a first section of the first memory, metadata from a metadata portion of the first section in the first memory, the metadata from the metadata portion encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in the second memory;

analyzing the data location information in the retrieved metadata from the metadata portion of the first section in the first memory to determine whether the first section in the first memory currently contains data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request,

writing the block of data corresponding to the system memory section to the first section in the first memory; and

indicating, to the processor, a completion of writing the block of data.

17. The method of claim 16 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received request; and

writing the block of data to the second section in the first memory or the memory location in the second memory; and

indicating, to the processor, a completion of writing the block of data.

18. The method of claim 16 , further comprising:

in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received request,

further analyzing the data location information in the retrieved metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received request;

maintaining data currently in the first section in the first memory;

writing the block of data to the second section in the first memory or the memory location in the second memory; and

indicating, to the processor, a completion of writing the block of data.

19. The method of claim 17 wherein:

the metadata from the metadata portion includes one or more bits; and

the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more bits; and

determining whether the identified combination corresponds to the system memory section in the received request.

20. The method of claim 17 wherein:

the metadata from the metadata portion includes one or more Error Checking and Correction (ECC) bits; and

the data location information includes combinations of the one or more ECC bits that individually correspond to one of the multiple system memory sections; and

analyzing the data location information includes:

identifying a combination of the one or more ECC bits; and

determining whether the identified combination of ECC bits corresponds to the system memory section in the received request.