Network device safety protocol

1. A network device, comprising packet processing circuitry including:

at least one interface configured to receive packets; and

packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to:

assign input-output port specific sequence numbers to the respective packets in a first stage of packet processing by the packet processing circuitry responsively to respective input-output port combinations of the respective packets;

check for missing input-output port specific sequence numbers among the assigned input-output port specific sequence numbers in a second stage of packet processing by the packet processing circuitry after the first stage of packet processing by the packet processing circuitry in which the input-output port specific sequence numbers were assigned;

find missing ones of the respective packets in the second stage of the packet processing responsively to the missing input-output port specific sequence numbers; and

report the missing packets.

2. The device according to claim 1 , further comprising a silicon chip including the packet processing circuitry, the at least one interface including a plurality of ports, ones of the ports configured to be input ports, and others of the ports configured to be output ports, the silicon chip being configured to verify behavioral integrity of the silicon chip from the input ports to the output ports.

3. The device according to claim 1 , wherein:

the at least one interface includes a plurality of ports, ones of the ports configured to be input ports;

the input ports are configured to receive the packets and assign input-port-specific sequence numbers to the received packets; and

the packet forwarding circuitry is configured to find missing ones of the received packets responsively to checking for missing input-port-specific sequence numbers among the assigned input-port-specific sequence numbers.

4. The device according to claim 1 , wherein:

the at least one interface includes a plurality of ports, ones of the ports configured to be output ports to forward one of the packets;

the packet forwarding circuitry is configured to assign output-port-specific sequence numbers to processed ones of the packets; and

the output ports are configured to find missing ones of the processed packets responsively to checking for missing output-port-specific sequence numbers among the assigned output-port-specific sequence numbers.

5. The device according to claim 1 , wherein:

the at least one interface includes a plurality of ports, ones of the ports configured to be input ports to receive the packets, and one of the ports configured to be output ports to forward ones of the packets; and

the packet forwarding circuitry is configured to:

receive the respective packets from the input ports; and

make respective forwarding decisions for the respective packets to determine respective ones of the output ports to which to forward the respective packets.

6. The device according to claim 5 , wherein:

the input ports are configured to assign input-port-specific sequence numbers to the received packets; and

the packet forwarding circuitry is configured to find missing ones of the received packets responsively to checking for missing input-port-specific sequence numbers among the assigned input-port-specific sequence numbers.

7. The device according to claim 6 , wherein:

the packet forwarding circuitry is configured to assign output-port-specific sequence numbers to processed ones of the packets after the second stage of the packet processing; and

the output ports are configured to find missing ones of the processed packets responsively to checking for missing output-port-specific sequence numbers among the assigned output-port-specific sequence numbers.

8. The device according to claim 7 , wherein:

the input ports are configured to assign ingress timestamps to the received packets; and

the output ports are configured to:

find delayed ones of the packets exceeding a given processing delay in the packet processing responsively to checking respective ones of the ingress timestamps against a current time; and

report the delayed packets exceeding the given processing delay.

9. The device according to claim 1 , wherein:

each of the received packets includes a respective integrity check code;

the packet processing circuitry is configured to check the integrity check code of respective ones of the received packets; and

report ones of the packets failing the integrity check.

10. The device according to claim 1 , wherein:

the at least one interface includes a plurality of ports;

ones of the ports are configured to be input ports to receive the packets and assign ingress timestamps to the received packets;

one of the ports are configured to be output ports and to:

forward ones of the packets;

find delayed ones of the packets exceeding a given processing delay in the packet processing responsively to checking respective ones of the ingress timestamps against a current time; and

report the delayed packets exceeding the given processing delay.

11. The device according to claim 1 , wherein the at least one interface is configured to be connected to a data packet network.

12. The device according to claim 1 , wherein the at least one interface includes: a network interface configured to be connected to a data packet network; and a peripheral bus interface configured to be connected to a host device.

13. A networking method, comprising:

receiving packets;

making respective forwarding decisions for respective ones of the packets;

assigning input-output port specific sequence numbers to the respective packets in a first stage of packet processing by the packet processing

circuitry responsively to respective input-output port combinations of the respective packets;

checking for missing input-output port specific sequence numbers among the assigned input-output port specific sequence numbers in a second stage of packet processing by the packet processing circuitry after the first stage of packet processing by the packet processing circuitry in which the input-output port specific sequence numbers were assigned;

finding missing ones of the respective packets in the second stage of the packet processing responsively to the missing input-output port specific sequence numbers; and

reporting the missing packets.

14. The method according to claim 13 , wherein:

the assigning includes assigning input-port-specific sequence numbers to the received packets; and

the finding includes finding missing ones of the received packets responsively to checking for missing input-port-specific sequence numbers among the assigned input-port-specific sequence numbers.

15. The method according to claim 13 , wherein:

the assigning includes assigning output-port-specific sequence numbers to processed ones of the packets; and

the finding includes finding missing ones of the processed packets responsively to checking for missing output-port-specific sequence numbers among the assigned output-port-specific sequence numbers.

16. The method according to claim 13 , wherein the making includes making respective forwarding decisions for the respective packets to determine respective output ports to which to forward the respective packets.

17. The method according to claim 16 , wherein:

the assigning includes assigning input-port-specific sequence numbers to the received packets; and

the finding includes finding missing ones of the received packets responsively to checking for missing input-port-specific sequence numbers among the assigned input-port-specific sequence numbers.

18. The method according to claim 17 , wherein:

the assigning includes assigning output-port-specific sequence numbers to processed ones of the packets after the second stage of the packet processing; and

the finding includes finding missing ones of the processed packets responsively to checking for missing output-port-specific sequence numbers among the assigned output-port-specific sequence numbers.

19. The method according to claim 18 , further comprising:

assigning ingress timestamps to the received packets;

finding delayed ones of the packets exceeding a given processing delay in the packet processing responsively to checking respective ones of the ingress timestamps against a current time; and

reporting the delayed packets exceeding the given processing delay.

20. The method according to claim 13 , wherein each of the received packets includes a respective integrity check code, the method further comprising:

checking the integrity check code of respective ones of the received packets; and

reporting ones of the packets failing the integrity check.

21. The method according to claim 13 , further comprising:

assigning ingress timestamps to the received packets;

forwarding ones of the packets;

finding delayed ones of the packets exceeding a given processing delay in the packet processing responsively to checking respective ones of the ingress timestamps against a current time; and

reporting the delayed packets exceeding the given processing delay.