IP Library › Granted Patent US 11,848,327
Granted Patent B2
US 11,848,327 · App. 17/373,255 · Granted Dec 19, 2023

Integrated circuit device including a power supply line and method of forming the same

Inventors: Yi-Hsiung Lin (Hsinchu County, TW); Shang-Wen Chang (Hsinchu County, TW); Yi-Hsun Chiu (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/0886H01L21/823431H01L21/823475H01L23/50H01L27/0207
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Quick Facts
Patent No.
US 11,848,327
App. No.
17/373,255
Granted
Dec 19, 2023
Kind
B2
Abstract

A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Claims (58)

1. A method, comprising:

forming a first device fin structure and a second device fin structure on a substrate, the first device fin structure being laterally adjacent to the second device fin structure;

depositing a first dielectric layer on the first device fin structure and the second device fin structure, the first dielectric layer defining a trench disposed between the first device fin structure and the second device fin structure;

forming a power supply line in the trench and directly on a top surface of a portion of the first dielectric layer;

forming a source feature and a drain feature on the first device fin structure and the second device fin structure, respectively;

forming a source contact to couple the source feature to the power supply line, the source contact including:

a first portion contacting a top surface of the source feature; and

a second portion extending from a peripheral region of the first portion towards the power supply line to physically contact the power supply line.

2. The method of claim 1 , wherein a top surface of the power supply line is recessed in comparison to the top surface of the source feature.

3. The method of claim 1 , wherein forming the source contact includes:

forming a fill fin over the power supply line, the fill fin being disposed between the source feature and the drain feature;

depositing a second dielectric layer over the first dielectric layer, the source feature, the drain feature, and the fill fin;

removing portions of the fill fin and the second dielectric layer to form a slot opening, the slot opening exposing the top surface of the source feature and a portion of a top surface of the power supply line; and

depositing one or more conductive materials in the slot opening.

4. The method of claim 3 , wherein removing portions of the fill fin and the second dielectric layer to form the slot opening comprises an anisotropic etch process.

5. The method of claim 4 , wherein the anisotropic etch process uses a fluorine-containing etchant, a chlorine-containing etchant, or a combination thereof.

6. The method of claim 3 , wherein a material of the fill fin is different from a material of the first dielectric layer.

7. The method of claim 1 , wherein a sidewall of the second portion of the source contact is aligned with a sidewall of the power supply line.

8. A method, comprising:

providing a workpiece comprising a first fin structure and a second fin structure over a substrate, the first fin structure being parallel to the second fin structure;

conformally depositing a first dielectric layer over the first fin structure, the second fin structure and the substrate to define a trench between the first fin structure and the second fin structure;

forming a conductive line in the trench;

depositing a second dielectric layer over the conductive line and the first dielectric layer;

selectively recessing the first dielectric layer to expose a portion of the first fin structure and a portion of the second fin structure;

forming a first epitaxial feature over the exposed portion of the first fin structure and a second epitaxial feature over the exposed portion of the second fin structure;

depositing a third dielectric layer over the first epitaxial feature and the second epitaxial feature; and

forming a source/drain contact to couple the first epitaxial feature and the conductive line.

9. The method of claim 8 , wherein the conductive line comprises:

a barrier layer in direct contact with the first dielectric layer;

a seed layer disposed over the barrier layer; and

a conductive material disposed over the seed layer.

10. The method of claim 9 , wherein the conductive material comprises tungsten, although other suitable materials such as aluminum, copper, tungsten nitride, platinum, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, or a combination thereof.

11. The method of claim 8 , further comprising:

after the depositing of the second dielectric layer, planarizing the workpiece to expose the first dielectric layer and the second dielectric layer.

12. The method of claim 8 , wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer.

13. The method of claim 8 ,

wherein the first dielectric layer comprises silicon oxides, silicon nitrides, silicon carbides, fluoro-silicate glass (FSG), low-K dielectric materials, or a combination thereof

wherein the second dielectric layer comprises hafnium oxide, zirconium oxide, or aluminum oxide.

14. The method of claim 8 , wherein the selectively recessing forms a fill fin disposed directly over the conductive line.

15. The method of claim 14 , wherein the forming of the source/drain contact comprises:

forming an opening to expose the first epitaxial feature and a portion of the conductive line.

16. The method of claim 15 , wherein the forming of the opening comprises removing a portion of the fill fin.

17. A method, comprising:

providing a workpiece that includes a first fin and a second fin disposed side-by-side over a substrate;

conformally depositing a first dielectric layer over the first fin, the second fin and the substrate to define a trench between the first fin and the second fin;

forming a power supply line in the trench;

depositing a second dielectric layer over the power supply line and the first dielectric layer;

selectively recessing the first dielectric layer to expose a portion of the first fin and a portion of the second fin;

forming a source feature over the exposed portion of the first fin structure and a drain feature over the exposed portion of the second fin structure;

forming a source contact to electrically couple the source feature to the power supply line; and

forming a drain contact directly over the drain feature.

18. The method of claim 17 , wherein the drain contact is insulated from the power supply line.

19. The method of claim 17 , further comprising:

after the forming of the drain contact, depositing a fourth dielectric layer over the source contact and the drain contact; and

forming a drain contact via through the fourth dielectric layer to couple to the drain contact.

20. The method of claim 17 ,

wherein the selectively recessing forms a fill fin disposed directly over the conductive line,

wherein a portion of the source contact is disposed between the fill fin and the first dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2021
From: LIN, YI-HSIUNG; CHANG, SHANG-WEN; CHIU, YI-HSUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 056827/0062 →
Continuity (3)
Division 16583438 · Sep 26, 2019
Provisional Application 62753728 · Oct 31, 2018
Related Publication 20210343712A1 · Nov 4, 2021