Semiconductor memory devices

1. A semiconductor memory device, comprising:

a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells;

a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction; and

a plurality of dummy active regions in the dummy cell region, each of the plurality of dummy active regions extending in the long axis direction, each of the plurality of dummy active regions having a second maximum width greater than a first maximum width in the short axis direction.

2. The semiconductor memory device of claim 1 , wherein at least one of the plurality of dummy active regions defines a plurality of sidewall recesses on sidewalls of the plurality of dummy active regions.

3. The semiconductor memory device of claim 2 , wherein the plurality of active regions are apart from each other at a first interval in the long axis direction and each extend in the long axis direction with a first length.

4. The semiconductor memory device of claim 3 , wherein the plurality of sidewall recesses are on the sidewalls of the at least one of the plurality of dummy active regions apart from each other with a second length in the long axis direction, and

the plurality of sidewall recesses have a first value of a second interval in the long axis direction.

5. The semiconductor memory device of claim 4 , wherein a sum of the first length and the first interval is substantially the same as a sum of the second length and the second interval.

6. The semiconductor memory device of claim 2 , wherein the plurality of sidewall recesses are on all of the sidewalls of the plurality of dummy active regions.

7. The semiconductor memory device of claim 2 , wherein the plurality of sidewall recesses are at sidewalls of a portion adjacent to the plurality of active regions among the plurality of dummy active regions, and

the plurality of sidewall recesses are not at sidewalls of a portion not adjacent to the plurality of active regions.

8. The semiconductor memory device of claim 2 , further comprising:

a device isolation structure defining the plurality of active regions and the plurality of dummy active regions,

wherein portions of the device isolation structure between two active regions adjacent to each other in the long axis direction among the plurality of active regions and the plurality of sidewall recesses are collinear along a plurality of horizontal lines arranged at equal intervals in the second horizontal direction.

9. The semiconductor memory device of claim 1 , wherein the plurality of active regions repeat with a first pitch in the short axis direction, and

the plurality of dummy active regions repeat with a second pitch greater than the first pitch in the short axis direction.

10. The semiconductor memory device of claim 9 , wherein a ratio of the second maximum width to the first maximum width is greater than a ratio of the second pitch to the first pitch.

11. A semiconductor memory device, comprising:

a substrate comprising a memory cell region, a peripheral region and a dummy cell region between the memory cell region and the peripheral region, the memory cell region including a plurality of memory cells, the dummy cell region including a plurality of dummy memory cells;

a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction, and the plurality of active regions repeat with a first pitch in the short axis direction, the short axis direction orthogonal to the long axis direction;

at least one logic active region in the peripheral region; and

a plurality of dummy active regions in the dummy cell region, each of the plurality of dummy active regions extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width, and the plurality of dummy active regions repeat with a second pitch twice the first pitch, the second width and the second pitch in the short axis direction, wherein

at least one of the plurality of dummy active regions defines a plurality of sidewall recesses on sidewalls of the at least one of the plurality of dummy active regions.

12. The semiconductor memory device of claim 11 , further comprising:

a plurality of word lines extending parallel to each other in the first horizontal direction across the plurality of active regions and the plurality of dummy active regions; and

a plurality of bit lines extending parallel to each other in the second horizontal direction, the plurality of bit lines on the substrate, wherein

at least two of the plurality of dummy active regions are arranged in the first horizontal direction between the memory cell region and the peripheral region.

13. The semiconductor memory device of claim 11 , wherein the plurality of active regions are apart from each other at a first interval in the long axis direction, each of the plurality of active regions extending in the long axis direction and having a first length,

the plurality of sidewall recesses are on the sidewalls of the at least one of the plurality of dummy active regions apart from each other and having a second length in the long axis direction, the plurality of sidewall recesses having a first value of a second interval in the long axis direction, and

a sum of the first length and the first interval is substantially the same as a sum of the second length and the second interval.

14. The semiconductor memory device of claim 13 , wherein the first length is the same as the second length, and the first interval is the same as the second interval.

15. The semiconductor memory device of claim 11 , further comprising:

a device isolation structure defining the plurality of active regions, the plurality of dummy active regions, and the at least one logic active region,

wherein portions of the device isolation structure between two active regions adjacent to each other in the long axis direction among the plurality of active regions and the plurality of sidewall recesses are arranged in a honeycomb.

16. The semiconductor memory device of claim 15 , wherein the device isolation structure fills the plurality of sidewall recesses.

17. The semiconductor memory device of claim 11 , wherein the plurality of sidewall recesses are at the sidewalls of a portion adjacent to the plurality of active regions among the plurality of dummy active regions, and are not at the sidewalls of a portion adjacent to the at least one logic active region.

18. A semiconductor memory device, comprising:

a substrate comprising a memory cell region, a peripheral region, and a dummy cell region between the memory cell region and the peripheral region;

a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width, and the plurality of active regions repeat with a first pitch, the first width and the first pitch in a short axis direction orthogonal to the long axis direction;

at least one logic active region disposed in the peripheral region;

a plurality of dummy active regions in the dummy cell region, each of the plurality of dummy active regions extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width, and the plurality of dummy active regions repeat with a second pitch greater than the first pitch, the first width and the second width in the short axis direction;

a device isolation structure defining the plurality of active regions, the at least one logic active region, and the plurality of dummy active regions;

a plurality of word lines extending parallel to each other in the first horizontal direction across the plurality of active regions and the plurality of dummy active regions;

a plurality of bit lines that extending parallel to each other in the second horizontal direction, the plurality of bit lines on the substrate;

a plurality of buried contacts filling a lower portion of a space between the plurality of bit lines on the substrate;

a plurality of landing pads filling an upper portion of the space between the plurality of bit lines and extending onto the plurality of bit lines; and

a plurality of capacitors connected to the plurality of landing pads, wherein

at least one of the plurality of dummy active regions defines a plurality of sidewall recesses filled with the device isolation structure on sidewalls of the at least one of the plurality of dummy active regions.

19. The semiconductor memory device of claim 18 , wherein the second pitch is twice the first pitch, and

a ratio of the second width to the first width is greater than a ratio of the second pitch to the first pitch.

20. The semiconductor memory device of claim 18 , wherein the first pitch is 0.1 μm to 1 μm, and the second pitch is 0.2 μm to 2 μm.