Systems and methods for reconfiguring dual-function cell arrays
A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.
1. An integrated circuit die element comprising:
a field-programmable gate array (FPGA) including one or more FPGA elements, each of the one or more FPGA elements having a configuration based on configuration data;
a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array portions, each reconfigurable memory array portion being capable of configuration and reconfiguration as a storage memory array portion at one time or as a control logic array portion at a different time, the reconfigurable memory array portion configured to store process data when the reconfigurable memory array portion is configured as the storage memory array portion, the reconfigurable memory array portion configured to store the configuration data for controlling the configuration of at least a portion of the one or more FPGA elements when the reconfigurable memory array portion is configured as the control logic array portion; and
a control logic circuit functioning to configure each reconfigurable memory array portion as the respective memory array portion at the one time and as the respective logic array portion at the different time.
2. The integrated circuit die element of claim 1 , wherein the reconfigurable dual function memory array includes:
a first reconfigurable memory array portion configured as the storage memory array portion, and
a second reconfigurable memory array portion configured as the control logic array portion.
3. The integrated circuit die element of claim 1 , wherein the storage memory array portion comprises cache memory.
4. The integrated circuit die element of claim 1 , wherein the control logic circuit functions to configure at least one reconfigurable memory array portion after manufacturing and deployment of the integrated circuit die element.
5. The integrated circuit die element of claim 1 , wherein the control logic circuit functions to switch a particular reconfigurable memory array portion from the storage memory array portion to the control logic array portion.
6. The integrated circuit die element of claim 1 , wherein the control logic circuit functions to switch a particular reconfigurable memory array portion from the control logic array portion to the storage memory array portion.
7. The integrated circuit die element of claim 1 , wherein the integrated circuit die element comprises a stack of integrated circuit dies, the stack including a first reconfigurable dual function memory array die and a microprocessor die.
8. The integrated circuit die element of claim 7 , wherein the stack further comprises a second reconfigurable dual function memory array die.
9. The integrated circuit die element of claim 7 , wherein the stack further comprises an FPGA die or memory die.
10. A method comprising:
storing, by a control logic circuit, a first control value;
configuring, based on the first control value, at least one reconfigurable memory array portion of a reconfigurable dual function memory array as a storage memory array portion or as a control logic array portion, each reconfigurable memory array portion of the reconfigurable dual function memory array being capable of configuration and reconfiguration as the storage memory array portion at one time or as the control logic array portion at a different time, the reconfigurable memory array portion configured to store process data when the reconfigurable memory array portion is configured as the storage memory array portion, the reconfigurable memory array portion configured to store configuration data for controlling configuration of one or more field-programmable gate array (FPGA) elements of an FPGA when the reconfigurable memory array portion is configured as the control logic array portion;
obtaining, by the control logic circuit, a second control value; and
reconfiguring, based on the second control value, the at least one reconfigurable memory array portion.
11. The method of claim 10 , wherein the reconfigurable dual function memory array includes:
a first reconfigurable memory array portion configured as the storage memory array portion, and
a second reconfigurable memory array portion configured as the control logic array portion.
12. The method of claim 10 , wherein the storage memory array comprises cache memory.
13. The method of claim 10 , wherein the control logic circuit functions to configure at least one reconfigurable memory array portion after manufacturing and deployment of the integrated circuit die element.
14. The method of claim 10 , further comprising:
switching, by the control logic circuit, a particular memory array portion from the storage memory array portion to the control logic array portion.
15. The method of claim 10 , further comprising:
switching, by the control logic circuit, a particular control logic array portion from the control logic array portion to the storage memory array portion.
16. The method of claim 10 , wherein the integrated circuit die element comprises a stack of integrated circuit dies, the stack including a first reconfigurable dual function memory array die and a microprocessor die.
17. The method of claim 16 , wherein the stack further comprises a second reconfigurable dual function memory array die.
18. The method of claim 16 , wherein the stack further comprises an FPGA die or memory die.