In-memory compute array with integrated bias elements

1. A system, comprising:

processing circuitry; and

a memory coupled to the processing circuitry, the memory including an in-memory-compute (IMC) device having:

a first plurality of cells arranged as a plurality of rows of cells intersecting a plurality of columns of cells;

a plurality of computation engines, each computation engine respectively formed in a different one of a second plurality of cells, the second plurality of cells being formed from cells of the first plurality of cells, each computation engine formed at a respective row and column intersection; and

a plurality of bias engines, which, in operation, computationally combine outputs of the plurality of computation engines with respective bias values.

2. The system of claim 1 wherein a portion of the first plurality of cells comprises an array of memory bitcells.

3. The system of claim 2 wherein the array of memory bitcells is a static random access memory (SRAM) memory array.

4. The system of claim 1 wherein at least one of the plurality of computation engines, in operation, performs a gating operation.

5. The system of claim 1 wherein at least one of the plurality of computation engines, in operation, performs a mathematical operation.

6. The system of claim 1 , comprising one or more sensors coupled to the processing circuitry.

7. The system of claim 1 wherein the processing circuitry comprises one or more functional logic circuits.

8. The system of claim 1 , comprising a second memory coupled to the processing circuitry, wherein the second memory, in operation, stores instructions executable by the processing circuitry.

9. The system of claim 8 , wherein the processing circuitry, in operation, executes the stored instructions and the stored instructions comprise learning machine code.

10. An in-memory compute (IMC) method, comprising:

storing a plurality of values in respective memory bitcells of an in-memory compute memory device, wherein the in-memory compute memory device has a first plurality of cells arranged as a plurality of rows of cells intersecting a plurality of columns of cells, each cell of the first plurality of cells identifiable by its corresponding row and column;

performing a plurality of in-memory compute operations, each of the in-memory compute operations using one or more of the stored plurality of values as an operand;

storing results of the plurality of in-memory compute operations in a second plurality of cells, the second plurality of cells being formed from cells of the first plurality of cells; and

computationally combining results of the plurality of in-memory compute operations with respective bias values.

11. The IMC method of claim 10 wherein a portion of the in-memory compute memory device is a static random access memory (SRAM) memory device.

12. The IMC method of claim 10 wherein the plurality of in-memory compute operations include at least one gating function and at least one mathematical function.

13. The IMC method of claim 10 wherein computationally combining results of the plurality of in-memory compute operations with respective bias values includes:

combining a row of results information with a row of bias values.

14. The IMC method of claim 10 wherein computationally combining results of the plurality of in-memory compute operations with respective bias values includes:

producing a set of computationally combined values; and

storing the set of computationally combined values in memory bitcells of the first plurality of cells without passing the set of computationally combined values out of the in-memory compute memory device.

15. The IMC method of claim 10 wherein computationally combining results of the plurality of in-memory functions with respective bias values includes:

producing a set of computationally combined values;

storing the set of computationally combined values in memory bitcells of the first plurality of cells; and

passing at least some of the set of computationally combined values out of the in-memory compute memory device.

16. An in-memory compute (IMC) device, comprising:

a compute array having a first plurality of cells, the compute array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, each cell of the first plurality of cells identifiable by its corresponding row and column, wherein, in operation, the first plurality of cells store a plurality of values;

a plurality of computation engines, each computation engine respectively formed in a different one of a second plurality of cells, the second plurality of cells being formed from cells of the first plurality of cells, each computation engine formed at a respective row and column intersection, wherein in operation, the second plurality of cells perform a plurality of in-memory compute operations, each of the in-memory compute operations using one or more of the stored plurality of values as an operand; and

a plurality of bias engines, which, in operation, computationally combine outputs of the plurality of computation engines with respective bias values.

17. The IMC device of claim 16 wherein the plurality of in-memory compute operations include at least one gating function and at least one mathematical function.

18. The IMC device of claim 16 wherein computationally combining outputs of the plurality of computation engines with respective bias values includes:

combining a row of results information with a row of bias values.

19. The IMC device of claim 16 wherein computationally combining computationally combining outputs of the plurality of computation engines with respective bias values includes:

producing a set of computationally combined values; and

storing the set of computationally combined values in memory bitcells of the first plurality of cells.

20. The IMC device of claim 19 wherein computationally combining outputs of the plurality of computation engines with respective bias values includes:

passing at least some of the set of computationally combined values out of the in-memory compute memory device.