Storage device including nonvolatile memory device and method of operating the same

1. A method of operating a nonvolatile memory device, comprising:

dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups;

generating time-difference information comprising a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups;

generating offset information comprising a plurality of offset values corresponding to differences between a plurality of first read voltages and a plurality of corrected read voltages;

generating a plurality of second read voltages corresponding to a read address based on the offset information and the time-difference information; and

performing a read operation to read data from the nonvolatile memory device based on the read address and the plurality of second read voltages.

2. The method of claim 1 , further comprising performing a zoned namespace (ZNS) write scheme such that each of the plurality of memory blocks respectively stores data corresponding to a single application.

3. A storage device comprising:

a nonvolatile memory device comprising a plurality of memory blocks; and

a storage controller configured to control the nonvolatile memory device,

wherein the storage controller is configured to:

divide a memory block of the plurality of memory blocks into a plurality of retention groups;

generate time-difference information comprising a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups;

generate offset information comprising a plurality of first offset values corresponding to differences between a plurality of first read voltages and a plurality of corrected read voltages;

generate a plurality of second read voltages corresponding to a read address based on the offset information and the time-difference information; and

perform a read operation to read data from the nonvolatile memory device based on the read address and the plurality of second read voltages.

4. The storage device of claim 3 , wherein the storage controller is further configured to:

extract target offset values of the memory block corresponding to the read address;

extract a target EPI value of a target retention group, from among the plurality of retention groups, corresponding to the read address;

generate a plurality of second offset values by providing the target offset values and the target EPI value to an artificial neural network; and

generate the plurality of second read voltages by respectively adding the plurality of second offset values to the plurality of first read voltages corresponding to the read address.

5. The storage device of claim 4 , wherein the storage controller is further configured to train the artificial neural network based on training EPI values and measured offset values corresponding to the training EPI values.

6. The storage device of claim 4 , wherein the storage controller is further configured to:

receive, by the artificial neural network, only the target offset values among the plurality of first offset values which correspond to a plurality of bits of the memory block; and

output, by the artificial neural network, the plurality of second offset values corresponding to the target offset values.

7. The storage device of claim 4 , wherein the storage controller is further configured to:

receive, by the artificial neural network, each of the plurality of first offset values; and

output, by the artificial neural network, the plurality of second offset values corresponding to the plurality of first offset values.

8. The storage device of claim 4 , wherein the storage controller is further configured to provide, to the artificial neural network, the target offset values, the target EPI value, and any one or any combination of a block number of a target memory block corresponding to the read address and a program-erase cycle value corresponding to the read address.

9. The storage device of claim 3 , wherein the plurality of retention groups comprises a reference retention group having an EPI value of zero, and

wherein the plurality of first offset values of the memory block correspond to the reference retention group.

10. The storage device of claim 9 , wherein the plurality of corrected read voltages corresponding to the reference retention group are equal to the plurality of second read voltages.

11. The storage device of claim 3 , wherein the storage controller is further configured to:

perform the read operation based on the plurality of first read voltages before the plurality of first offset values corresponding to the read address are generated; and

perform the read operation based the plurality of second read voltages after the plurality of first offset values corresponding to the read address are generated.

12. The storage device of claim 11 , wherein the storage controller is further configured to:

perform a valley search operation to update the plurality of corrected read voltages, based on the read operation performed using the plurality of first read voltages or the read operation using the plurality of second read voltages failing; and

perform the read operation based on updated corrected read voltages that are updated by the valley search operation.

13. The storage device of claim 12 , wherein the storage controller is further configured to update the offset information of a target memory block corresponding to the read address using the updated corrected read voltages based on the read operation performed using the updated corrected read voltages being completed successfully.

14. The storage device of claim 13 , wherein the storage controller is further configured to update the time-difference information such that an EPI value of a target retention group corresponding to the read address becomes zero based on the read operation performed using the updated corrected read voltages being completed successfully.

15. The storage device of claim 3 , wherein the storage controller is further configured to store the time-difference information in the nonvolatile memory device based on a command to power off the storage device.

16. The storage device of claim 15 , wherein the storage controller is further configured to delete the offset information based on the command to power off the storage device.

17. The storage device of claim 15 , wherein the storage controller is further configured to read the time-difference information from the nonvolatile memory device based on the storage device being powered on.

18. The storage device of claim 3 , wherein the storage controller is further configured to perform a zoned namespace (ZNS) write scheme such that each of the plurality of memory blocks respectively stores data corresponding to a single application.

19. The storage device of claim 3 , wherein the storage controller is further configured to generate the plurality of second read voltages using an artificial neural network that is trained based on training EPI values and measured offset values corresponding to the training EPI values.

20. A storage device comprising:

a nonvolatile memory device; and

a storage controller configured to:

divide a memory block, from among a plurality of memory blocks of the nonvolatile memory device, into a plurality of retention groups;

generate time-difference information comprising a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups;

generate offset information comprising a plurality of first offset values corresponding to differences between a plurality of first read voltages and a plurality of corrected read voltages;

train an artificial neural network based on training EPI values and measured offset values corresponding to the training EPI values;

generate a plurality of second offset values by providing the offset information and the time-difference information to the artificial neural network;

generate a plurality of second read voltages by respectively adding the plurality of first offset values to the plurality of first read voltages; and

perform a read operation to read data from the nonvolatile memory device based on a read address and the plurality of second read voltages.