IP Library › Granted Patent US 12,075,608
Granted Patent B2
US 12,075,608 · App. 17/377,790 · Granted Aug 27, 2024

Multi-gate semiconductor device for memory and method for forming the same

Inventor: Huai-Ying Huang (Taipei County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H10B10/125G11C11/412
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Quick Facts
Patent No.
US 12,075,608
App. No.
17/377,790
Granted
Aug 27, 2024
Kind
B2
Abstract

A memory device includes a first SRAM cell, a second SRAM cell, a first inter transistor and a second inter transistor. The first SRAM cell includes two first pull-up transistors, two first pull-down transistors, and two first pass-gate transistors. The second SRAM cell includes two second pull-up transistors, two second pull-down transistors, and two second pass-gate transistors. The first inter transistor and the second inter transistor are electrically connected to the first SRAM cell and the second SRAM cell.

Claims (44)

1. A memory device comprising:

a first static random access memory (SRAM) cell comprising:

a first pull-up transistor and a second pull-up transistor;

a first pull-down transistor and a second pull-down transistor; and

a first pass-gate transistor and a second pass-gate transistor;

a second SRAM cell comprising:

a third pull-up transistor and a fourth pull-up transistor;

a third pull-down transistor and a fourth pull-down transistor; and

a third pass-gate transistor and a fourth pass-gate transistor;

a first inter transistor and a second inter transistor electrically connected to the first SRAM cell and the second SRAM cell;

a first bit line coupled to the first pass-gate transistor of the first SRAM cell;

a second bit line coupled to the fourth pass-gate transistor of the second SRAM cell; and

a third bit line coupled to the second pass-gate transistor of the first SRAM and the third pass-gate transistor of the second SRAM,

wherein a source/drain of the first inter transistor is electrically connected to a source/drain of the second pull-up transistor of the first SRAM cell and a source/drain of the second pass-gate transistor of the first SRAM cell, and a source/drain of the second inter transistor is electrically connected to a source/drain of the third pull-up transistor of the second SRAM cell and a source/drain of the third pass-gate transistor of the second SRAM cell.

2. The memory device of claim 1 , wherein the first inter transistor and the second inter transistor are electrically connected in series.

3. The memory device of claim 2 , wherein the first inter transistor is electrically connected to a source/drain of the second pull-down transistor of the first SRAM cell, and the second inter transistor is electrically connected to a source drain of the third pull-down transistor of the second SRAM.

4. The memory device of claim 1 , wherein the inter transistors are p-type field-effect transistor (pFET) devices.

5. The memory device of claim 1 , wherein the first pull-up transistor and the second pull-up transistor of the first SRAM cell and the third pull-up transistor and the fourth pull-up transistor of the second SRAM cell are pFET devices.

6. The memory device of claim 1 , wherein the first pull-down transistor and the second pull-down transistor of the first SRAM cell and the third pull-down transistor and the fourth transistor of the second SRAM cell are n-type field-effect transistor (nFET) devices.

7. The memory device of claim 1 , wherein the first pass-gate transistor and the second pass-gate transistor of the first SRAM cell and the third pass-gate transistor and the fourth pass-gate transistor of the second SRAM cell are nFET devices.

8. The memory device of claim 1 , wherein the source/drain of the first inter transistor is electrically connected to the source/drain of the second pull-up transistor of the first SRAM cell and the source/drain of the second inter transistor in series, and the source/drain of the second inter transistor is electrically connected to the source/drain of the third pull-up transistor of the second SRAM in series.

9. A multi-gate semiconductor device for memory comprising:

a first memory cell comprising a plurality of first multi-gate FET devices, wherein the plurality of first multi-gate FET devices comprises at least a first pass-gate transistor, a second pass-gate transistor, a first pull-up transistor and a second pull-up transistor;

a second memory cell comprising a plurality of second multi-gate FET devices, wherein the plurality of second multi-gate FET devices comprises at least a third pass-gate transistor, a fourth pass-gate transistor, a third pull-up transistor and a fourth pull-up transistor;

a third memory cell comprising a plurality of third multi-gate FET devices, wherein the plurality of third multi-gate FET devices comprises at least a fifth pass-gate transistor, a sixth pass-gate transistor, a fifth pull-up transistor and a sixth pull-up transistor;

a first fin structure coupled to the second pull-up transistor of the first memory cell and the fourth pull-up transistor of the second memory cell; and

a second fin structure coupled to the first pull-up transistor of the first memory cell and the fifth pull-up transistor of the third memory cell.

10. The multi-gate semiconductor device of claim 9 , wherein the first fin structure and the second fin structure are parallel to each other.

11. The multi-gate semiconductor device of claim 9 , wherein a length of the first fin structure and a length of the second fin structure are substantially the same.

12. The multi-gate semiconductor device of claim 9 , wherein each of the first fin structure and the second fins structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers, and the first semiconductor layers and the second semiconductor layers are alternately stacked over the substrate.

13. The multi-gate semiconductor device of claim 12 , wherein the first semiconductor layer comprises a first semiconductor material and a second semiconductor material, the second semiconductor layer comprises the second semiconductor material, and a lattice constant of the first semiconductor material is different from a lattice constant of the second semiconductor material.

14. The multi-gate semiconductor device of claim 9 , wherein a layout pattern of the first memory cell and a layout pattern of the second memory cell are line symmetrical about a first axis, and the layout pattern of the first memory cell and a layout pattern of the third memory cell are line symmetrical about a second axis.

15. The multi-gate semiconductor device of claim 14 , wherein the first axis and the second axis are parallel to each other.

16. A multi-gate semiconductor device for memory comprising:

a first memory cell comprising a plurality of first multi-gate FET devices, wherein the plurality of first multi-gate FET devices comprises at least a first pass-gate transistor, a second pass-gate transistor, a first pull-up transistor and a second pull-up transistor;

a second memory cell comprising a plurality of second multi-gate FET devices, wherein the plurality of second multi-gate FET devices comprises at least a third pass-gate transistor, a fourth pass-gate transistor, a third pull-up transistor and a fourth pull-up transistor;

a third memory cell comprising a plurality of third multi-gate FET devices, wherein the plurality of third multi-gate FET devices comprises at least a fifth pass-gate transistor, a sixth pass-gate transistor, a fifth pull-up transistor and a sixth pull-up transistor;

a first fin structure coupled to the second pull-up transistor of the first memory cell and the fourth pull-up transistor of the second memory cell and extending along a first direction; and

a second fin structure coupled to the first pull-up transistor of the first memory cell and the third pull-up transistor of the third memory cell and extending along the first direction,

wherein a layout pattern of the first memory cell and a layout pattern of the second memory cell are line symmetrical about a first axis, the layout pattern of the first memory cell and a layout pattern of the third memory cell are line symmetrical about a second axis, and the first axis and the second axis extend along a second direction perpendicular to the first direction.

17. The multi-gate semiconductor device of claim 16 , wherein a length of the first fin structure and a length of the second fin structure are substantially the same.

18. The multi-gate semiconductor device of claim 16 , wherein the first multi-gate FET devices of the first memory cell comprise two first pull-down FET devices, the second multi-FET devices of the second memory cell comprise two second pull-down FET devices, and the third multi-gate FET devices of the third memory cell comprise two third pull-down FET devices.

19. The multi-gate semiconductor device of claim 13 , wherein the first semiconductor layer is channel layers of the first pull-up transistor and the second pull-up transistor of the first memory cell, channel layers of the third pull-up transistor and the fourth pull-up transistor of the second memory cell, and channel layer of the fifth pull-up transistor and the sixth pull-up transistor of the third memory cell.

20. The multi-gate semiconductor device of claim 13 , wherein the second semiconductor layer is channel layers of the first pass-gate transistor and the second pass-gate transistor of the first memory cell, channel layers of the third pass-gate transistor and the fourth pass-gate transistor of the second memory cell, and channel layer of the fifth pass-gate transistor and the sixth pass-gate transistor of the third memory cell.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2021
From: HUANG, HUAI-YING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 056880/0986 →
Continuity (1)
Related Publication 20230015575A1 · Jan 19, 2023