FinFET SRAM cells with dielectric fins

1. An integrated circuit (IC), the IC comprising: an SRAM cell oriented lengthwise along a first direction and widthwise along a second direction generally perpendicular to the first direction, wherein the first SRAM cell includes:

a first, a second, a third, a fourth, and a fifth dielectric fins disposed in this order along the first direction and oriented lengthwise along the second direction, wherein the first and the fifth dielectric fins define two edges of the first SRAM cell, and wherein the first, the second, the third, the fourth, and the fifth dielectric fins are disposed in isolation structures over a substrate;

a first p-type semiconductor fin structure disposed between the first and the second dielectric fins;

a second p-type semiconductor fin structure disposed between the fourth and the fifth dielectric fins;

a first n-type semiconductor fin structure disposed between the second and the third dielectric fins,

a second n-type semiconductor fin structure disposed between the third and the fourth dielectric fins,

wherein the first and the second p-type semiconductor fin structures and the first and the second n-type semiconductor fin structures are oriented lengthwise along the second direction and separated from each of the first, second, third, fourth, and fifth dielectric fins by portions of the isolation structures; and

gate structures oriented lengthwise along the first direction and spaced from each other along the second direction, wherein the gate structures engage one or more of the first, the second, the third, the fourth, and the fifth dielectric fins, the first and the second n-type semiconductor fin structures, and the first and the second p-type semiconductor fin structures;

wherein portions of the first, the second, the third, the fourth, and the fifth dielectric fins disposed under the gate structures have a first height, wherein portions of the first, the second, the third, the fourth, and the fifth dielectric fin not disposed under the gate structures have a second height, and wherein the first height is greater than the second height.

2. The IC of claim 1 , wherein each of the first and the second p-type semiconductor fin structures includes two p-type semiconductor fins, and wherein each of the first and the second n-type semiconductor fin structures consists of one n-type semiconductor fin.

3. The IC of claim 1 , wherein each of the first and the second p-type semiconductor fin structures consists of one p-type semiconductor fin, and wherein each of the first and the second n-type semiconductor fin structures consists of one n-type semiconductor fin.

4. The IC of claim 1 , further comprising:

a first source/drain (S/D) feature disposed over the first p-type semiconductor fin structure;

a second S/D feature disposed over the second p-type semiconductor fin structure;

a third S/D feature disposed over the first n-type semiconductor fin structure;

a fourth S/D feature disposed over the second n-type semiconductor fin structure;

a first S/D contact physically contacting the first S/D feature, the third S/D feature, and the second dielectric fin; and

a second S/D contact physically contacting the second S/D feature, the fourth S/D feature, and the fourth dielectric fin.

5. The IC of claim 4 , wherein both of the first and the third S/D features physically contact the second dielectric fin, wherein both of the second and the fourth S/D features physically contact the fourth dielectric fin, and wherein both of the third and the fourth S/D features physically contacting the third dielectric fin.

6. The IC of claim 1 , wherein the gate structures engage with the first p-type semiconductor fin structure to form a first pull-down (PD) transistor and a first pass-gate (PG) transistor, wherein the gate structures engage with the second p-type semiconductor fin structure to form a second PD transistor and a second PG transistor, and wherein the gate structures engage with the first and the second n-type semiconductor fin structures to form a first pull-up (PU) transistor and a second PU transistor, respectively.

7. The IC of claim 1 , wherein an isolation structure surrounds a bottom portion of each of the first, second, third and fourth dielectric fins.

8. An integrated circuit (IC), the IC comprising:

an SRAM cell oriented lengthwise along a first direction and widthwise along a second direction generally perpendicular to the first direction, wherein the first SRAM cell includes:

a first, a second, a third, a fourth, and a fifth dielectric fins disposed in this order along the first direction and oriented lengthwise along the second direction, wherein the first and the fifth dielectric fins define two edges of the first SRAM cell, and wherein the first, second, third, fourth, and fifth dielectric fins are disposed in isolation structures over a substrate;

a first p-type semiconductor fin structure disposed between the first and the second dielectric fins;

a second p-type semiconductor fin structure disposed between the fourth and the fifth dielectric fins;

a first n-type semiconductor fin structure disposed between the second and the third dielectric fins,

a second n-type semiconductor fin structure disposed between the third and the fourth dielectric fins,

wherein the first and the second p-type semiconductor fin structures and the first and the second n-type semiconductor fin structures are oriented lengthwise along the second direction and separated from each of the first, the second, the third, the fourth, and the fifth dielectric fins by portions of the isolation structures;

a source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fin structures and the first and the second n-type semiconductor fin structures;

a first S/D contact disposed over and physically contacting the S/D epitaxial feature over the first p-type semiconductor fin structure, the S/D epitaxial feature over the first n-type semiconductor fin structure, and the second dielectric fin; and

a second S/D contact disposed over and physically contacting the S/D epitaxial feature over the second p-type semiconductor fin structure, the S/D epitaxial feature over the second n-type semiconductor fin structure, and the fourth dielectric fin.

9. The IC of claim 8 , wherein each of the first and the second p-type semiconductor fin structures includes the same number of fins as each of the first and the second n-type semiconductor fin structures.

10. The IC of claim 8 , wherein each of the first and the second p-type semiconductor fin structures includes one more fin than each of the first and the second n-type semiconductor fin structures.

11. The IC of claim 10 , wherein each of the first and the second p-type semiconductor fin structures includes two fins and each of the first and the second n-type semiconductor fin structures consists of one fin, and wherein the S/D epitaxial feature disposed over each of the first and the second p-type semiconductor fin structures merges the two fins together.

12. The IC of claim 8 , wherein the first S/D contact separates each sidewall of the second dielectric fin from the S/D epitaxial features over the first p-type and the first n-type semiconductor fin structures, and wherein the second S/D contact separates each sidewall of the fourth dielectric fin from the S/D epitaxial features over the second p-type and the second n-type semiconductor fin structures.

13. The IC of claim 8 , wherein a top surface of each of the first, the second, the third, the fourth, and the fifth dielectric fins is below a widest portion of each S/D epitaxial feature.

14. The IC of claim 8 , wherein a sidewall of each of the first, the second, the third, the fourth, and the fifth dielectric fins physically contacts a widest portion of each S/D epitaxial feature.

15. The IC of claim 8 , wherein the SRAM cell is a first SRAM cell, the IC further comprising:

a second SRAM cell disposed next to the first SRAM cell along the second direction, wherein layout of the second SRAM cell is a mirror image of layout of the first SRAM cell with respect to a first imaginary boundary line along the first direction;

a third SRAM cell disposed next to the second SRAM cell along the first direction, wherein layout of the third SRAM cell is a mirror image of the layout of the second SRAM cell with respect to a second imaginary boundary line going through the fourth dielectric fin lengthwise; and

a fourth SRAM cell disposed next to the third SRAM cell along the second direction and next to the first SRAM cell along the first direction, wherein layout of the fourth SRAM cell is a mirror image of the layout of the first SRAM cell with respect to the second imaginary boundary line.

16. An integrated circuit (IC), the IC comprising:

a first SRAM cell oriented lengthwise along a first direction and widthwise along a second direction generally perpendicular to the first direction, wherein the first SRAM cell includes:

a first boundary fin, a first inner fin, a second inner fin, a third inner fin, and a second boundary dielectric fin disposed in this order along the first direction and oriented lengthwise along the second direction, wherein the first boundary, the first inner, the second inner, the third inner, and second boundary dielectric fins are disposed in isolation structures over a substrate;

first and second p-type semiconductor fins disposed between the first boundary and the first inner dielectric fins;

third and fourth p-type semiconductor fins disposed between the third inner and the second boundary dielectric fins;

a first n-type semiconductor fin disposed between the first inner and the second inner dielectric fins,

a second n-type semiconductor fin disposed between the second inner and the third inner dielectric fins,

wherein the first and the second p-type semiconductor fins and the first and the second n-type semiconductor fins are oriented lengthwise along the second direction and separated from each of the first boundary, the first inner, the second inner, the third inner, and second boundary dielectric fins by portions of the isolation structures;

first source/drain (S/D) epitaxial features each merging the first and the second p-type semiconductor fins and the third and the fourth p-type semiconductor fins, respectively;

second S/D epitaxial features disposed over each of the first and the second n-type semiconductor fins;

a first S/D contact physically contacting with the first S/D epitaxial feature, the second S/D epitaxial feature, and the first inner dielectric fin; and

a second S/D contact physically contacting with the first S/D epitaxial feature over the second p-type semiconductor fin structure, the second S/D epitaxial feature, and the third inner dielectric fin.

17. The IC of claim 16 , wherein the first inner dielectric fin physically contacts each of the first and the second S/D epitaxial features, wherein the second inner dielectric fin physically contacts each of the second S/D epitaxial features, and wherein the third inner dielectric fin physically contacts each of the first and the second S/D epitaxial features.

18. The IC of claim 16 , wherein each of the first, the second, and the third inner dielectric fins is physically separated from each of the first and the second S/D epitaxial features.

19. The IC of claim 18 , wherein a top surface of each of the first, the second, and the third inner dielectric fins is lower than a widest portion of each of the first and the second S/D epitaxial features.

20. The IC of claim 16 , further comprising gate structures engaged with some of the first boundary, the first inner, the second inner, the third inner, and second boundary dielectric fins, wherein the dielectric fins not engaged with the gate structures are lower than the dielectric fins engaged with the gate structures.