IP Library Granted Patent US 11,817,420
Granted Patent B2
US 11,817,420 · App. 17/379,568 · Granted Nov 14, 2023

Systems and methods for direct bonding in semiconductor die manufacturing

Inventors: Chia Jung Hsu (Taichung, TW); Eiichi Nakano (Boise, ID)
Assignee: Micron Technology, Inc.
H01L24/80H01L24/05H01L25/0657H01L2224/05647H01L2224/8012H01L2224/80948H01L2225/06541
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Quick Facts
Patent No.
US 11,817,420
App. No.
17/379,568
Granted
Nov 14, 2023
Kind
B2
Abstract

A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms an electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.

Claims (34)

1. A method for bonding a first semiconductor die to a second semiconductor die to form a stacked semiconductor device, the method comprising:

aligning a first plurality of metallic bond sites on a first surface of the first semiconductor die with a second plurality of metallic bond sites on a second surface of the second semiconductor die;

bonding the first surface to the second surface, wherein the first plurality of metallic bond sites is electrically connected to the second plurality of bond sites after the bonding, wherein the bonding leaves at least one void between the first surface and the second surface, and wherein a metal material extends at least partially along an inner surface of the void; and

exposing the stacked semiconductor device to radiation to excite a chemical constituent in the void, wherein the excited chemical constituent reacts with the metal material along the inner surface of the void to reduce an electrical conductivity of the metal material.

2. The method of claim 1 wherein the chemical constituent includes a hydroxy group molecule, wherein exposing the stacked semiconductor device to microwave radiation excites the hydroxy group molecule, and wherein the excited hydroxy group molecule reacts with the metal material along the inner surface of the void to oxidize the metal material.

3. The method of claim 1 wherein first plurality of metallic bond sites and the second plurality of bond sites comprise copper.

4. The method of claim 1 wherein the first surface and the second surface comprise a dielectric material.

5. The method of claim 4 , wherein the dielectric material is selected from silicon dioxide, silicon nitride, silicon carbon nitride, and silicon carbon oxide.

6. The method of claim 4 wherein the first surface is bonded directly to the second surface by a hybrid bonding process.

7. The method of claim 1 wherein the radiation is microwave radiation having a frequency between 900 megahertz (MHz) and 2450 MHz.

8. A method for bonding layers in a stacked semiconductor device, the method comprising:

aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate;

annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate, wherein the annealing results in at least one void between the upper surface and the lower surface, wherein the void includes a layer of diffused metal extending from a first individual bond pad from the first array of bond pads towards a second individual bond pad from the first array of bond pads; and

exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.

9. The method of claim 8 wherein a particle is positioned between the first semiconductor substrate and the second semiconductor substrate, and wherein the particle causes the void to form during the annealing.

10. The method of claim 8 wherein the excited chemical constituent reacts with the layer of diffused metal in the void to reduce an electrical conductivity of the layer of diffused metal.

11. The method of claim 8 wherein the chemical constituent includes a hydroxy group molecule, wherein exposing the stacked semiconductor device to microwave radiation excites the hydroxy group molecule, and wherein the excited hydroxy group molecule reacts with the layer of diffused metal in the void to oxidize the layer of diffused metal.

12. The method of claim 11 wherein the chemical constituent is atmospheric air and wherein the hydroxy group molecule is dihydrogen oxide.

13. The method of claim 11 wherein the layer of diffused metal in the void includes copper.

14. The method of claim 8 , wherein:

the first semiconductor substrate is a first dielectric layer on top of a first semiconductor die;

the second semiconductor substrate is a second dielectric layer on top of a second semiconductor die; and

the annealing bonds the first dielectric layer directly onto the second dielectric layer.

15. A stacked semiconductor device comprising:

a first semiconductor die having a first surface and a second surface opposite the first surface, the first semiconductor die including two first bond pads positioned on the first surface;

a second semiconductor die having a third surface directly contacting the first surface of the first semiconductor die and a fourth surface opposite the third surface, the second semiconductor die including two second bond pads positioned on the third surface, wherein each of the two second bond pads are electrically coupled to a corresponding one of the two first bond pads at two respective interfaces at the third surface; and

a void between the first surface and the third surface and positioned laterally between the two interfaces, wherein the void includes a layer of diffused and oxidized metal extending from at least one of the first bond pads, and wherein the diffused and oxidized metal is electrically non-conductive.

16. The stacked semiconductor device of claim 15 wherein void includes a gas having a hydroxy group compound that can be excited by the microwave process, and wherein the layer of diffused metal is oxidized as a result of a reaction between the layer of diffused metal and the excited hydroxy group compound.

17. The stacked semiconductor device of claim 15 wherein the void further includes gaseous water that can be excited by the microwave process to react with the layer of diffused metal.

18. The stacked semiconductor device of claim 15 wherein the void further is caused by a particle on the third surface of the second semiconductor die when the third surface is bonded to the first surface of the first semiconductor die.

19. The stacked semiconductor device of claim 15 wherein:

the first semiconductor die further includes two first interconnect structures electrically coupled to the two first bond pads and extending towards the second surface; and

the second semiconductor die further includes two second interconnect structures electrically coupled to the two second bond pads and extending towards the fourth surface.

20. The stacked semiconductor device of claim 15 wherein the layer of diffused and oxidized metal is intentionally oxidized by a microwave process after bonding the first semiconductor die to the second semiconductor die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2021
From: HSU, CHIA JUNG; NAKANO, EIICHI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 056904/0730 →
Continuity (1)
Related Publication 20230020037A1 · Jan 19, 2023