IP Library Granted Patent US 11,709,597
Granted Patent B2
US 11,709,597 · App. 17/379,607 · Granted Jul 25, 2023

Memory system and method for controlling nonvolatile memory

Inventors: Hideki Yoshida (Yokohama Kanagawa, JP); Shinichi Kanno (Tokyo, JP)
Assignee: Kioxia Corporation
G06F3/061G06F3/064G06F3/0616G06F3/0658G06F3/0688G06F12/0246G06F12/1009G06F2212/1016G06F2212/1024G06F2212/1036G06F2212/2022G06F2212/7201G06F2212/7205G06F2212/7207G06F2212/7208
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Quick Facts
Patent No.
US 11,709,597
App. No.
17/379,607
Filed
Jul 19, 2021
Granted
Jul 25, 2023
Kind
B2
Art Unit
2132
USPC
711/5
Abstract

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

Claims (60)

1. A memory system connectable to a host, comprising:

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation; and

a controller electrically connected to the nonvolatile memory and configured to:

manage a plurality of super blocks, each of the plurality of super blocks including at least one block of the plurality of blocks;

in response to receiving a write request from the host, the write request designating a first super block identifier and a first logical identifier,

select a first super block corresponding to the first super block identifier from the plurality of super blocks;

determine a first location in the first super block;

write first data to the first location in the first super block, the first data being associated with the first logical identifier; and

update a first table such that a first in-block physical address corresponding to the first location is mapped to the first logical identifier, the first table mapping between logical identifiers and in-block physical addresses of the first super block but not mapping between the logical identifiers and physical addresses of the plurality of super blocks.

2. The memory system according to claim 1 , wherein

the first table is one of a plurality of tables, each of the plurality of tables corresponding to a super block identifier, and the controller is further configured to:

in updating the first table, select the first table from the plurality of tables based on the first super block identifier.

3. The memory system according to claim 1 , wherein

the controller is further configured to inform the host of a super block identifier that is allocated for use by the host.

4. The memory system according to claim 1 , wherein

the controller is further configured to:

in response to receiving a read request from the host, the read request designating the first super block identifier and the first logical identifier,

acquire the first in-block physical address by referring to the first table; and

read data associated with the first logical identifier from the nonvolatile memory, based at least on the acquired first in-block physical address.

5. The memory system according to claim 1 , wherein

the controller is further configured to:

in response to receiving a control command from the host, the control command designating a copy source super block identifier and a copy destination super block identifier,

select a second super block and a third super block from the plurality of super blocks, the second super block corresponding to the copy source super block identifier, the third super block corresponding to the copy destination super block identifier; and

copy valid data from a copy source location in the second super block to a copy destination location in the third super block.

6. The memory system according to claim 5 , wherein

the controller is further configured to:

update a second table mapping between logical identifiers and in-block physical addresses of the second super block, and a third table mapping between logical identifiers and in-block physical addresses of the third super block, such that an in-block physical address mapped to a logical identifier of the valid data is changed from a second in-block physical address indicative of the copy source location in the second super block to a third in-block physical address indicative of the copy destination location of the third super block.

7. The memory system according to claim 6 , wherein

each of the plurality of blocks includes a plurality of pages, and

the second in-block physical address is represented by a second in-block offset indicating an offset from a leading part of the second super block to the copy source location by a multiple of a grain, and the third in-block physical address is represented by a third in-block offset indicating an offset from a leading part of the third super block to the copy destination location by a multiple of the grain, the grain having a size different from a size of each of the plurality of pages.

8. The memory system according to claim 5 , wherein

the controller is further configured to

notify the host of a logical identifier of the valid data and the copy destination super block identifier to which the valid data is copied.

9. A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, the method comprising:

managing a plurality of super blocks, each of the plurality of super blocks including at least one block of the plurality of blocks;

in response to receiving a write request from the host, the write request designating a first super block identifier and a first logical identifier,

selecting a first super block corresponding to the first super block identifier from the plurality of super blocks;

determining a first location in the first super block;

writing first data to the first location in the first super block, the first data being associated with the first logical identifier; and

updating a first table such that a first in-block physical address corresponding to the first location is mapped to the first logical identifier, wherein the first table maps between logical identifiers and in-block physical addresses of the first super block but does not map between the logical identifiers and physical addresses of the plurality of super blocks.

10. The method according to claim 9 , wherein

the first table is one of a plurality of tables, each of the plurality of tables corresponding to a super block identifier, and the method further comprises:

in updating the first table, selecting the first table from the plurality of tables based on the first super block identifier.

11. The method according to claim 9 further comprising:

informing the host of a super block identifier that is allocated for use by the host.

12. The method according to claim 9 further comprising:

in response to receiving a read request from the host, the read request designating the first super block identifier and the first logical identifier,

acquiring the first in-block physical address by referring to the first table; and

reading data associated with the first logical identifier from the nonvolatile memory, based at least on the acquired first in-block physical address.

13. The method according to claim 9 further comprising:

in response to receiving a control command from the host, the control command designating a copy source super block identifier and a copy destination super block identifier,

selecting a second super block and a third super block from the plurality of super blocks, the second super block corresponding to the copy source super block identifier, the third super block corresponding to the copy destination super block identifier; and

copying valid data from a copy source location in the second super block to a copy destination location in the third super block.

14. The method according to claim 13 further comprising:

updating a second table mapping between logical identifiers and in-block physical addresses of the second super block, and a third table mapping between logical identifiers and in-block physical addresses of the third super block, such that an in-block physical address mapped to a logical identifier of the valid data is changed from a second in-block physical address indicative of the copy source location in the second super block to a third in-block physical address indicative of the copy destination location of the third super block.

15. The method according to claim 14 , wherein

each of the plurality of blocks includes a plurality of pages, and

the second in-block physical address is represented by a second in-block offset indicating an offset from a leading part of the second super block to the copy source location by a multiple of a grain, and the third in-block physical address is represented by a third in-block offset indicating an offset from a leading part of the third super block to the copy destination location by a multiple of the grain, the grain having a size different from a size of each of the plurality of pages.

16. The method according to claim 13 further comprising:

notifying the host of a logical identifier of the valid data and the copy destination super block identifier to which the valid data is copied.

Assignments (3)
MERGER AND CHANGE OF NAME Recorded Feb 17, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: K.K. PANGEA
Reel/Frame 059039/0780 →
CHANGE OF NAME Recorded Feb 17, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 059175/0001 →
CHANGE OF NAME Recorded Feb 17, 2022
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 059180/0266 →
Priority Claims (1)
JP 2017-181447 · Sep 21, 2017 · national
Continuity (3)
Continuation 16660870 · Oct 23, 2019
Continuation 15914009 · Mar 7, 2018
Related Publication 20210349632A1 · Nov 11, 2021