Peripheral component interconnect express interface device and system including the same

1. A peripheral component interconnect express (PCIe) interface device, comprising:

a No Operation (NOP) data link layer packet (DLLP) generator configured to generate a NOP DLLP including event information representing a trigger point of a dump operation, event in response to occurrence of an event; and

a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes,

wherein the event information is used to specify an occurrence time of the event.

2. The PCIe interface device according to claim 1 , wherein the NOP DLLP is discarded in response to a data integrity check, and

wherein the NOP DLLP includes a support field including a plurality of bits and the NOP DLLP generator represents the event information by setting at least one bit of the support field of the NOP DLLP.

3. The PCIe interface device according to claim 2 , wherein the NOP DLLP generator generates the NOP DLLP in which the bits in the support field of the NOP DLLP respectively correspond to a plurality of events.

4. The PCIe interface device according to claim 2 , wherein the NOP DLLP generator generates the NOP DLLP corresponding to a single event using all of the bits in the support field of the NOP DLLP.

5. The PCIe interface device according to claim 1 , wherein the transmitter repeatedly transmits the NOP DLLP during a preset time period.

6. The PCIe interface device according to claim 1 , further comprising:

a register storage configured to store data, transmitted and received during a preset time period including the occurrence time of the event, and information about a communication environment in response to the occurrence of the event.

7. The PCIe interface device according to claim 1 , wherein the event includes at least one of reduction of lanes due to a timeout of a link training and status state machine (LTSSM), occurrence of link-down due to the timeout of the LTSSM, occurrence of an internal parity error, completion of post-processing of a parity error, performance of a temperature rise prevention operation caused due to a temperature rise, and termination of the temperature rise prevention operation caused due to the temperature rise.

8. A peripheral component interconnect express (PCIe) system, comprising:

a first PCIe device configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing a trigger point of a dump operation, in response to occurrence of an event, and to transmit the NOP DLLP through a link including a plurality of lanes; and

a second PCIe device configured to, when the NOP DLLP is received from the first PCIe device, perform the dump operation for storing information about data and packets transmitted and received during a set time period including a time at which the NOP DLLP is received,

wherein the event information is used to specify an occurrence time of the event.

9. The PCIe system according to claim 8 , wherein the NOP DLLP is discarded in response to a data integrity check, and

wherein the NOP DLLP includes a support field including a plurality of bits and the first PCIe device represents the event information by setting at least one bit of the support field of the NOP DLLP.

10. The PCIe system according to claim 9 , wherein the first PCIe device generates the NOP DLLP in which the bits in the support field of the NOP DLLP respectively correspond to a plurality of events.

11. The PCIe system according to claim 9 , wherein the first PCIe device generates the NOP DLLP corresponding to a single event using all of the bits in the support field of the NOP DLLP.

12. The PCIe system according to claim 8 , wherein the first PCIe device repeatedly transmits the NOP DLLP during a preset time period.

13. The PCIe system according to claim 8 , wherein the first PCIe device stores data, transmitted and received during a preset time period including the occurrence time of the event, and information about a communication environment in response to the occurrence of the event.

14. The PCIe system according to claim 8 , wherein the event includes at least one of reduction of lanes due to a timeout of a link training and status state machine (LTSSM), occurrence of link-down due to the timeout of the LTSSM, occurrence of an internal parity error, completion of post-processing of a parity error, performance of a temperature rise prevention operation caused due to a temperature rise, and termination of the temperature rise prevention operation caused due to the temperature rise.

15. A peripheral component interconnect express (PCIe) system, comprising:

a first PCIe device configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing a trigger point of a dump operation, in response to occurrence of an event, and to transmit the NOP DLLP through a link including a plurality of lanes;

a second PCIe device coupled to the first PCIe device through the link and configured to transmit and receive a packet including the NOP DLLP to and from the first PCIe device; and

a protocol analyzer coupled to the link and configured to monitor the packet transmitted and received between the first PCIe device and the second PCIe device through the link and to perform the dump operation for storing information about a communication environment based on the event information when detecting the NOP DLLP,

wherein the event information is used to specify an occurrence time of the event.

16. The PCIe system according to claim 15 , wherein the NOP DLLP is discarded in response to a data integrity check, and

wherein the NOP DLLP includes a support field including a plurality of bits and the first PCIe device represents the event information by setting at least one bit of the support field of the NOP DLLP.

17. The PCIe system according to claim 16 , wherein the first PCIe device generates the NOP DLLP in which the bits in the support field of the NOP DLLP respectively correspond to a plurality of events.

18. The PCIe system according to claim 16 , wherein the first PCIe device generates the NOP DLLP corresponding to a single event using all of the bits in the support field of the NOP DLLP.

19. The PCIe system according to claim 15 , wherein the first PCIe device stores data, transmitted and received during a preset time period including the occurrence time of the event, and information about a communication environment in response to the occurrence of the event.

20. The PCIe system according to claim 15 , wherein the event includes at least one of reduction of lanes due to a timeout of a link training and status state machine (LTSSM), occurrence of link-down due to the timeout of the LTSSM, occurrence of an internal parity error, completion of post-processing of a parity error, performance of a temperature rise prevention operation caused due to a temperature rise, and termination of the temperature rise prevention operation caused due to the temperature rise.