System, device and method for accessing device-attached memory

1. A device connected to a host processor via a bus, the device comprising:

an accelerator circuit configured to operate based on a message received from the host processor; and

a controller configured to control access to a memory connected to the device,

wherein the device is configured to be set to a host bias mode or a device bias mode, and

wherein the controller is further configured to, in the host bias mode and in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory, and

wherein the prefetch comprises sending a command to the memory before receiving a second message from the host processor in response to the first message.

2. The device of claim 1 , wherein the controller, in response to the read request in the device bias mode, is further configured to:

read the first data from the memory, and

provide the first data to the accelerator circuit.

3. The device of claim 1 , wherein the controller is further configured to receive the second message from the host processor, wherein the second message indicates completion of the resolution of coherence, and provide the first data to the accelerator circuit in response to the second message.

4. The device of claim 3 , wherein the controller is further configured to provide the first message to the host processor via the bus based on a first protocol and receive the second message from the host processor via the bus based on a second protocol, and

wherein the host processor is configured to access the memory through the bus and the controller based on the second protocol.

5. The device of claim 1 , further comprising a buffer configured to store a copy of the first data that is prefetched,

wherein the controller is further configured to provide the copy of the first data stored in the buffer to the accelerator circuit.

6. The device of claim 5 , wherein the buffer is further configured to store ready information indicating whether the copy of the first data stored in the buffer is valid, and

wherein the controller is further configured to, based on the ready information when the second message indicating completion of the resolution of coherence is received from the host processor, provide the copy of the first data stored in the buffer to the accelerator circuit or wait for reception of the first data from the memory.

7. The device of claim 1 , wherein the memory comprises a higher-level memory and a lower-level memory, and

wherein the controller is further configured to prefetch the first data by copying data from the lower-level memory to the higher-level memory as a copy of the first data.

8. The device of claim 7 , wherein the controller is further configured to provide the copy of the first data to the accelerator circuit in response to the second message indicating completion of the resolution of coherence, the second message being received from the host processor.

9. A system comprising:

a host processor comprising at least one core configured to execute instructions;

a device connected to the host processor via a bus and configured to be set to a host bias mode or a device bias mode; and

a memory connected to the device and configured to be accessed by the host processor through the device,

wherein the device is further configured to, in the host bias mode, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory before receiving, from the host processor, a second message indicating completion of the resolution of coherence, and

wherein the prefetch comprises sending a command to the memory before receiving the second message from the host processor.

10. The system of claim 9 , wherein the device is further configured to provide the first message to the host processor via the bus based on a first protocol and receive the second message from the host processor via the bus based on a second protocol, and

wherein the host processor is configured to access the memory through the bus and through the device based on the second protocol.

11. The system of claim 9 , wherein the device is further configured to, in the device bias mode, omit to provide the first message to the host processor and read the first data from the memory.

12. The system of claim 9 , wherein the memory comprises:

a higher-level memory; and

a lower-level memory, and

wherein the device is further configured to prefetch the first data by copying data from the lower-level memory to the higher-level memory.

13. The system of claim 9 , wherein the device comprises a buffer configured to store a copy of the first data that is prefetched, and

wherein the device is further configured to use the copy of the first data stored in the buffer when the second message is received from the host processor.

14. The system of claim 13 , wherein the buffer is further configured to store ready information indicating whether the copy of the first data stored in the buffer is valid, and

wherein the device is further configured to, based on the ready information when the second message is received from the host processor, use the copy of the first data stored in the buffer or wait for reception of the first data from the memory.

15. A method of operating a device connected to a host processor via a bus, the method comprising:

setting a host bias mode as a mode for accessing a memory connected to the device;

providing, to the host processor via the bus, a first message requesting resolution of coherence on a region in the memory corresponding to an address;

prefetching first data from the region in the memory based on the address, wherein the prefetching comprises sending a command to the memory before receiving a second message from the host processor in response to the first message; and

receiving, from the host processor via the bus, the second message indicating completion of the resolution of coherence on the region in the memory.

16. The method of claim 15 , further comprising detecting, from the memory, a trigger of a read on the region in the memory,

wherein the providing of the first message and the prefetching of the first data are performed in response to the detecting of the trigger.

17. The method of claim 15 , wherein the providing of the first message comprises providing the first message to the host processor based on a first protocol,

wherein the receiving of the second message comprises receiving the second message from the host processor based on a second protocol, and

wherein the method further comprises receiving a third message for accessing the memory, from the host processor based on the second protocol.

18. The method of claim 15 , wherein the prefetching of the first data comprises copying the first data from a lower-level memory included in the memory to a higher-level memory included in the memory.

19. The method of claim 15 , wherein the prefetching of the first data comprises:

reading the first data from the memory based on the address; and

storing a copy of the first data in a buffer included in the device.

20. The method of claim 19 , wherein the prefetching of the first data further comprises activating ready information when the copy of the first data is completely stored in the buffer, and

wherein the method further comprises, when the second message is received, using the copy of the first data stored in the buffer or waiting for a reception of the first data from the memory, based on the ready information.