Devices including stacked nanosheet transistors

1. A nanosheet transistor device comprising:

a transistor stack comprising:

a lower tri-gate nanosheet transistor having a first nanosheet width; and

an upper tri-gate nanosheet transistor on the lower tri-gate nanosheet transistor and having a second nanosheet width that is different from the first nanosheet width,

wherein the lower tri-gate nanosheet transistor comprises:

a pair of source/drain regions spaced apart from each other in a first direction;

at least one first nanosheet that is between the pair of source/drain regions and comprise four surfaces extending in the first direction; and

a lower gate in which three of the four surfaces of the at least one first nanosheet are located, wherein the lower gate does not overlay one of the four surfaces of the at least one first nanosheet viewed from a vantage point normal to the one of the four surfaces of the at least one first nanosheet, and wherein the upper tri-gate nanosheet transistor comprises:

at least one second nanosheet comprising four surfaces extending in the first direction; and

an upper gate, in which three of the four surfaces of the at least one second nanosheet are located, wherein the upper gate does not overlay one of the four surfaces of the at least one second nanosheet viewed from a vantage point normal to the one of the four surfaces of the at least one second nanosheet.

2. The nanosheet transistor device of claim 1 , wherein the lower gate is wider than the upper gate.

3. The nanosheet transistor device of claim 1 ,

wherein the at least one second nanosheet overlaps the at least one first nanosheet.

4. The nanosheet transistor device of claim 1 ,

wherein the lower gate comprises opposite first and second sidewalls,

wherein the upper gate comprises opposite third and fourth sidewalls,

wherein the third sidewall of the upper gate is aligned with the first sidewall of the lower gate, and

wherein the fourth sidewall of the upper gate overlaps the at least one first nanosheet.

5. The nanosheet transistor device of claim 4 ,

wherein the at least one first nanosheet is spaced apart from the first sidewall of the lower gate by metal of the lower gate, and

wherein the at least one second nanosheet is spaced apart from the third sidewall of the upper gate by metal of the upper gate.

6. The nanosheet transistor device of claim 1 ,

wherein the lower gate comprises opposite first and second sidewalls,

wherein the upper gate comprises opposite third and fourth sidewalls,

wherein the third sidewall of the upper gate is offset from the first sidewall of the lower gate, and

wherein the fourth sidewall of the upper gate overlaps the at least one first nanosheet.

7. The nanosheet transistor device of claim 6 ,

wherein the at least one first nanosheet is spaced apart from the second sidewall of the lower gate by metal of the lower gate, and

wherein the at least one second nanosheet is spaced apart from the third sidewall of the upper gate by metal of the upper gate.

8. The nanosheet transistor device of claim 3 , further comprising an insulation region that is on an upper surface of the lower gate and a sidewall of the upper gate.

9. The nanosheet transistor device of claim 8 , wherein the insulation region contacts the one of the four surfaces of the at least one second nanosheet and overlaps the at least one first nanosheet.

10. A nanosheet transistor device comprising:

a transistor stack comprising:

a lower nanosheet transistor having a first nanosheet width and a lower gate width; and

an upper nanosheet transistor on the lower nanosheet transistor and having a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively,

wherein the lower nanosheet transistor comprises:

a pair of source/drain regions spaced apart from each other in a first direction;

a first nanosheet that is between the pair of source/drain regions and comprises four surfaces extending in the first direction; and

a lower gate,

wherein the upper nanosheet transistor comprises:

a second nanosheet comprise four surfaces extending in the first direction; and

an upper gate,

wherein at least one of the lower nanosheet transistor or the upper nanosheet transistor is a tri-gate nanosheet transistor,

when the lower nanosheet transistor is a tri-gate nanosheet transistor, three of the four surfaces of the first nanosheet is in the lower gate, and the lower gate does not overlay one of the four surfaces of the first nanosheet viewed from a vantage point normal to the one of the four surfaces of the first nanosheet, and

when the upper nanosheet transistor is a tri-gate nanosheet transistor, three of the four surfaces of the second nanosheet is in the upper gate, and the upper gate does not overlay one of the four surfaces of the second nanosheet viewed from a vantage point normal to the one of the four surfaces of the second nanosheet.

11. The nanosheet transistor device of claim 10 , wherein each of the lower nanosheet transistor and the upper nanosheet transistor is a tri-gate nanosheet transistor.

12. The nanosheet transistor device of claim 11 , further comprising another transistor stack comprising tri-gate nanosheet transistors,

wherein the transistor stack and the another transistor stack are adjacent each other and have opposite fork-sheet directions from each other.

13. The nanosheet transistor device of claim 10 , wherein the lower nanosheet transistor and the upper nanosheet transistor are a gate-all-around (GAA) nanosheet transistor and a tri-gate nanosheet transistor, respectively, or vice versa.