Integrated circuit with nanosheet transistors with metal gate passivation

1. A method, comprising:

forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first gate all around transistor;

forming a plurality of second semiconductor nanosheets corresponding to channel regions of a second gate all around transistor;

forming a first trench in an interlevel dielectric layer above the semiconductor nanosheets;

depositing, in a first deposition process, a first interfacial dielectric layer on the first semiconductor nanosheets and a second interfacial dielectric layer on the second semiconductor nanosheets;

depositing, in a second deposition process, a first high-K dielectric layer on the first interfacial dielectric layer and a second high-K dielectric layer on the second interfacial dielectric layer;

depositing, in a third deposition process, a first layer of a first gate metal in direct contact with the first high-K dielectric layer and between the first semiconductor nanosheets and a second layer of the first gate metal in direct contact with the second high-K dielectric layer and between the second semiconductor nanosheets;

exposing the second high-K dielectric layer by removing the second layer of the first gate metal;

depositing, in a fourth deposition process, a first layer of a second gate metal in direct contact with the first layer of the first gate metal and a second layer of the second gate metal in direct contact with the second high-K dielectric layer;

depositing, in a fifth deposition process in-situ with the fourth deposition process, a first passivation layer in direct contact with the first layer of the second gate metal and a second passivation layer in direct contact with the second layer of the second gate metal; and

depositing, in a sixth deposition process, a metal gate fill material in direct contact with the first passivation layer and filling the first trench above the first semiconductor nanosheets.

2. The method of claim 1 , further comprising performing the fifth deposition process without breaking vacuum from the fourth deposition process.

3. The method of claim 2 , further comprising performing the fourth deposition process with a first atomic layer deposition process.

4. The method of claim 3 , further comprising performing the fifth deposition process with a second atomic layer deposition process without breaking the vacuum from the first atomic layer deposition process.

5. The method of claim 2 , further comprising:

performing the fourth deposition process in a first deposition chamber; and

performing the fifth deposition process in a second deposition chamber in fluid communication with the first deposition chamber.

6. The method of claim 1 , wherein the second passivation layer is positioned between the second semiconductor nanosheets.

7. The method of claim 1 , wherein a work function of the second gate all around transistor is greater than or equal to 4.9 eV.

8. A method, comprising:

forming a plurality of first semiconductor nanosheets corresponding to channel regions of an N-type gate all around transistor;

forming a plurality of second semiconductor nanosheets corresponding to channel regions of a P-type gate all around transistor;

forming a first trench in an interlevel dielectric layer above the first semiconductor nanosheets;

forming a second trench in the interlevel dielectric layer above the second semiconductor nanosheets;

depositing, with a first deposition process, a first interfacial dielectric layer on the first and a second interfacial dielectric layer on the second semiconductor nanosheets;

depositing, with a second deposition process, a first high-K dielectric layer on the first interfacial dielectric layer and a second high-K dielectric layer on the second interfacial dielectric layer;

depositing, with a third deposition process, a first layer of a first gate metal in direct contact with the first high-K dielectric layer and a second layer of the first gate metal in direct contact with the second high-K dielectric layer;

exposing the second high-K dielectric layer by removing the second layer of the first gate metal from the second high-K dielectric layer;

depositing, with a fourth deposition process, a first layer of a second gate metal in direct contact with the first layer of the first gate metal and a second layer of the second gate metal in direct contact with the second high-K dielectric layer;

depositing, with a fifth deposition process in-situ with the fourth deposition process, a first passivation layer in direct contact with the first layer of the second gate metal and a second passivation layer in direct contact with the second layer of the second gate metal; and

depositing, with a sixth deposition process, a first layer of a metal gate fill material in direct contact with the first passivation layer and filling the first trench, and a second layer of the metal gate fill material in contact with the second passivation layer and filling the second trench.

9. The method of claim 8 , further comprising:

covering the first layer of the first gate metal in photoresist at the N-type gate all around transistor;

removing the second layer of the first gate metal from the second high-K dielectric layer on the second semiconductor nanosheets while the first layer of the first gate metal is covered by the photoresist at the N-type gate all around transistor; and

removing the photoresist from the first layer of the first gate metal at the N-type gate all around transistor after removing the second layer of the first gate metal from the second high-K dielectric layer on the second semiconductor nanosheets.

10. The method of claim 9 , further comprising the fourth deposition process after removing the photoresist from the second layer of the first gate metal.

11. The method of claim 8 , wherein the second layer of the metal gate fill material and the second layer of the second gate metal correspond to a metal gate of the P-type gate all around transistor.

12. A method, comprising:

forming, in a first deposition process, a first gate dielectric layer on first channels of an N-type gate all around transistor and a second gate dielectric on second channels of a P-type gate all around transistor;

forming a first trench in an interlevel dielectric layer above the first channels;

forming a second trench in the interlevel dielectric layer above the second channels;

forming, in a second deposition process, a first layer of a first gate metal in direct contact with the first gate dielectric layer and a second layer of the first gate metal in direct contact with the second gate dielectric layer;

exposing the second gate dielectric layer by removing the second layer of the first gate metal;

forming, in a third deposition process, a first layer of a second gate metal in direct contact with the first layer of the first gate metal and a second layer of the second gate metal in direct contact the second gate dielectric layer;

forming, in a fourth deposition process in situ with the third deposition process, a first passivation layer in direct contact with the first layer of the second gate metal and a second passivation layer positioned directly on the second layer second gate metal; and

depositing, in a fifth deposition process, a first layer of a metal gate fill material in direct contact with the first passivation layer and a second layer of the metal gate fill material in contact with the second passivation layer.

13. The method of claim 12 , wherein the second layer of the second gate metal is positioned between the second channel regions.

14. The method of claim 13 , wherein the first gate metal includes carbon and one or more of titanium and tantalum.

15. The method of claim 14 , wherein the second gate metal includes nitrogen and one or more of titanium, tantalum, tungsten and molybdenum.

16. The method of claim 15 , wherein the first and second passivation layers include a different material than the second gate metal.

17. The method of claim 12 , wherein the second passivation layer is positioned between the second channel regions, wherein the first passivation layer is not positioned between the first channel regions.

18. The method of claim 1 , wherein the first and second passivation layers are a metal nitride.

19. The method of claim 18 , wherein the metal gate fill material is tungsten.

20. The method of claim 1 , wherein the first gate all around transistor is an N-type transistor and the second gate all around transistor is a P-type transistor.