Granted Patent B2

US 12,332,682 · App. 17/381,270 · Granted Jun 17, 2025

Inventors: Itamar Sivan (Tel Aviv, IL); Yonatan Cohen (Tel Aviv, IL); Nissim Ofek (Tel Aviv, IL); Asaf Rozen (Tel Aviv, IL); Guy Osi (Tel Aviv, IL); Ramon Szmuk (Bordeaux, FR)

Assignee: Q.M Technologies Ltd.

G06F1/12

Abstract

Claims (37)

1. A system for clock synchronization comprising:

a first processing unit operable at a first clock, wherein the first clock is provided by a system clock via a first variable delay;

a second processing unit operable at a second clock, wherein the second clock is provided by the system clock via a second variable delay; and

a sync line operably coupled between the first processing unit and the second processing unit, wherein:

the first processing unit is operable to send the first clock to the second processing unit via the sync line;

the second processing unit is operable to send the second clock to the first processing unit via the sync line;

the second processing unit is operable to generate a first phase difference between the first clock as received and the second clock;

the first processing unit is operable to generate a second phase difference between the second clock as received and the first clock;

the first variable delay is adjustable according to the first phase difference and the second phase difference; and

the second variable delay is adjustable according to the first phase difference and the second phase difference.

2. The system of claim 1 , wherein:

the first processing unit comprises a first sampling circuit that is operable according to a sample clock,

the second processing unit comprises a second sampling circuit that is operable according to the sample clock, and

the sample clock is at different frequency than the system clock.

3. The system of claim 2 , wherein a relationship between a sample clock frequency and a system clock frequency is known and configurable.

4. The system of claim 2 , wherein:

the first processing unit and the second processing unit each comprise digital logic operable to compute a phase difference between two clocks.

5. The system of claim 2 , wherein:

the first processing unit and the second processing unit each comprise an averaging circuit.

6. The system of claim 2 , wherein:

the first processing unit and the second processing unit are each operable to determine a duty cycle of a sampled first clock and a duty cycle of a sampled second clock.

7. The system of claim 1 , wherein a quantum orchestration platform (QOP) comprises the first processing unit and the second processing unit.

8. A method for clock synchronization comprising:

forwarding, via a cable, a first clock from a first processing unit to a second processing unit;

generating, at the second processing unit, a first phase difference between the first clock as received and a second clock;

forwarding, via the cable, the second clock from the second processing unit to the first processing unit;

generating, at the first processing unit, a second phase difference between the second clock as received and the first clock and;

adjusting, via a variable delay unit, one or both the first clock and the second clock, wherein the adjusting is according to the first phase difference and the second phase difference.

9. The method of claim 8 , wherein:

the first clock and the second clock are both at a common frequency,

generating the first phase difference and generating the second phase difference each comprise sampling with a third clock, and

the third clock is at a different frequency.

10. The method of claim 9 , wherein a relationship between a sample clock frequency and a system clock frequency is known and configurable.

11. The method of claim 9 , wherein generating the first phase difference and generating the second phase difference each comprise performing an exclusive OR operation between a sampled first clock and a sampled second clock.

12. The method of claim 11 , wherein generating the first phase difference and generating the second phase difference each comprise averaging an output of the exclusive OR operation.

13. The method of claim 9 , wherein generating the first phase difference and generating the second phase difference each comprise determining a duty cycle of a sampled first clock and a duty cycle of a sampled second clock.

14. The method of claim 8 , wherein a quantum orchestration platform (QOP) comprises the first processing unit and the second processing unit.

Assignments (7)

Continuity (1)

References Cited (201)