Method for testing a variable digital delay line and a device having variable digital delay line testing capabilities
A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
1. A method for testing a variable digital delay line that comprises multiple taps, the method comprises:
receiving, by a tap of the digital variable delay line and by a variable delay unit, an input signal;
finding, a first configuration for the variable delay unit that provides a delay from the variable delay unit that is closest in time and phase to a delay introduced by the tap;
wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
2. The method according to claim 1 , wherein the finding comprises comparing a signal from an output of the tap to a signal from an output of the variable delay unit.
3. The method according to claim 2 , wherein the finding further comprises setting multiple second configurations for the variable delay unit and finding for each second configuration a timing difference between a signal from an output of the tap to a signal from an output of the variable delay unit.
4. The method according to claim 2 , wherein the finding further comprises comparing by a phase detector, between a signal from an output of the tap provided via a first multiplexer to the phase detector and the input signal that is-provided via a second multiplexer to the variable delay unit, wherein output of the variable delay unit is provided to the phase detector.
5. The method according to claim 1 , wherein the finding comprises setting multiple second configurations for the variable delay unit and finding, for each of the second configurations, a timing difference between a signal from an output of the tap to a signal from an output of the variable delay unit.
6. The method according to claim 1 , wherein the finding comprises comparing by a phase detector, between a signal from an output of the tap that is provided via a first multiplexer to the phase detector and the input signal that is provided via a second multiplexer to the variable delay unit, wherein output of the variable delay unit is provided to the phase detector.
7. The method according to claim 1 , wherein the finding is followed by storing for the tap variable delay unit configuration information representative of the first configuration.
8. The method according to claim 1 , wherein the finding is followed by outputting to a device coupled to the test circuit, variable delay unit configuration information representative of the first configuration.
9. The method according to claim 1 , wherein the finding is followed by processing variable delay unit configuration information representative of the first configuration.
10. The method according to claim 1 , wherein the finding comprises sending a variable delay unit control signal to the variable delay unit, wherein the variable delay unit control signal controls a variable delay unit transfer characteristic in response to the variable delay control signal.
11. A device having variable digital delay line testing capabilities, the device comprises:
an integrated circuit that comprises:
a variable digital delay line including a-tap that receives an input signal; and
a variable delay unit coupled to a control circuit that receives the input signal;
wherein the control circuit is adapted to find first configuration for the variable delay unit, that provides a delay from the variable delay unit that is closest in time and phase to a delay introduced by the tap.
12. The device according to claim 11 , wherein the control circuit is further adapted to compare a phase of the input signal that has been delayed by the tap to a phase of the input signal that has been delayed by the variable delay unit.
13. The device according to claim 12 , wherein the control circuit is further adapted to set multiple second configurations for the variable delay unit and find for each second configuration a timing difference between a signal from an output of the tap to a signal from an output of-the variable delay unit.
14. The device according to claim 12 , wherein the variable delay unit comprises an input for receiving a variable delay unit control signal and an analog circuit adapted to set a value of an analog current that is provided to a part of the variable delay unit and controls its transfer characteristics.
15. The device according to claim 11 , wherein the control circuit is further adapted to set multiple second configurations for the variable delay unit and find, for each of the second configurations a timing difference between a signal from an output of the tap to a signal from an output of the variable delay unit.
16. The device according to claim 11 , wherein the control circuit comprises a phase detector, adapted to compare the phase of a signal from an output of the tap provided from a first multiplexer to the phase detector, and the phase of a signal from an output of the variable delay unit.
17. The device according to claim 11 , wherein the control circuit is adapted to generate-configuration information representative of the first configuration.
18. The device according to claim 11 , wherein the control circuit is adapted to output to another circuit that is coupled to the test circuit configuration information representative of the first configuration.
19. The device according to claim 11 , further adapted to process variable delay unit configuration information representative of the first.
20. The device according to claim 11 , wherein the variable delay unit comprises an input for receiving a variable delay unit control signal and an analog circuit adapted to set a value of an analog current that is provided to a part of the variable delay unit and controls its transfer characteristics.