IP Library › Granted Patent US 11,678,475
Granted Patent B2
US 11,678,475 · App. 17/381,462 · Granted Jun 13, 2023

Static random access memory using vertical transport field effect transistors

Inventors: Tsung-Sheng Kang (Ballston Lake, NY); Ardasheir Rahman (Schenectady, NY); Tao Li (Slingerlands, NY); Albert M. Young (Fishkill, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L27/1104H01L23/5286H01L27/092H01L29/7827
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Quick Facts
Patent No.
US 11,678,475
App. No.
17/381,462
Granted
Jun 13, 2023
Kind
B2
Abstract

A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Claims (36)

1. A memory device, comprising:

a first field effect transistor (FET) stack on a first bottom source/drain region, wherein the first field effect transistor (FET) stack includes a first vertical transport fin field effect transistor (VTFET) device between a second VTFET device and the first bottom source/drain region;

a second field effect transistor (FET) stack on a second bottom source/drain region, wherein the second field effect transistor (FET) stack includes a third VTFET device between a fourth VTFET device and the second bottom source/drain region;

a third field effect transistor (FET) stack on a third bottom source/drain region, wherein the third field effect transistor (FET) stack includes a fifth VTFET device between a sixth VTFET device and the third bottom source/drain region, wherein the third bottom source/drain region is laterally adjacent to the first bottom source/drain region and the second bottom source/drain region;

a first electrical connection interconnecting a gate structure of the third VTFET device with a gate structure of the fifth VTFET device; and

a second electrical connection interconnecting a gate structure of the second VTFET device with a gate structure of the sixth VTFET device.

2. The memory device of claim 1 , further comprising a first shared source/drain region between the first VTFET device and the second VTFET device; a second shared source/drain region between the third VTFET device and the fourth VTFET device; and a third shared source/drain region between the fifth VTFET device and the sixth VTFET device.

3. The memory device of claim 2 , further comprising a third electrical connection interconnecting the second shared source/drain region and the third bottom source/drain region.

4. The memory device of claim 3 , further comprising a fourth electrical connection interconnecting the first shared source/drain region and a top source/drain region on the sixth VTFET device.

5. The memory device of claim 4 , further comprising a fifth electrical connection interconnecting a gate structure of the first VTFET device with a gate structure of the fourth VTFET device, and a word line electrically connected to the fifth electrical connection.

6. The memory device of claim 5 , further comprising a bit line electrically connected to the first bottom source/drain region.

7. The memory device of claim 6 , further comprising a sixth electrical connection in electrical contact with the third shared source/drain region.

8. The memory device of claim 7 , wherein the first VTFET device, second VTFET device, third VTFET device, and fourth VTFET device are each n-type VTFET devices, and the fifth VTFET device and sixth VTFET device are each p-type VTFET devices.

9. The memory device of claim 8 , wherein the first shared source/drain region and the second shared source/drain region are each configured as drains, and the third shared source/drain region is configured as a source.

10. A memory device, comprising:

a first field effect transistor (FET) stack on a first bottom source/drain region, wherein the first field effect transistor (FET) stack includes a first vertical transport fin field effect transistor (VTFET) device between a second VTFET device and the first bottom source/drain region;

a second field effect transistor (FET) stack on a second bottom source/drain region, wherein the second field effect transistor (FET) stack includes a third VTFET device between a fourth VTFET device and the second bottom source/drain region, wherein the second bottom source/drain region is aligned with the first bottom source/drain region along a long axis;

a third field effect transistor (FET) stack on a third bottom source/drain region, wherein the third field effect transistor (FET) stack includes a fifth VTFET device between a sixth VTFET device and the third bottom source/drain region, wherein the third bottom source/drain region is laterally adjacent to the first bottom source/drain region and the second bottom source/drain region, and the third field effect transistor (FET) stack is positioned between the first field effect transistor (FET) stack and second field effect transistor (FET) stack;

a first electrical connection interconnecting a gate structure of the third VTFET device with a gate structure of the fifth VTFET device; and

a second electrical connection interconnecting a gate structure of the second VTFET device with a gate structure of the sixth VTFET device.

11. The memory device of claim 10 , wherein the first VTFET device, second VTFET device, third VTFET device, and fourth VTFET device are each n-type VTFET devices, and the fifth VTFET device and sixth VTFET device are each p-type VTFET devices.

12. The memory device of claim 11 , wherein the first shared source/drain region and the second shared source/drain region are each configured as drains, and the third shared source/drain region is configured as a source.

13. The memory device of claim 12 , further comprising a third electrical connection interconnecting a gate structure of the second VTFET device with a gate structure of the fourth VTFET device.

14. The memory device of claim 13 , further comprising a word line electrically connected to the third electrical connection.

15. The memory device of claim 14 , further comprising a ground electrically connected to the first bottom source/drain region and the second bottom source/drain region.

16. A memory device, comprising:

a first field effect transistor (FET) stack on a first bottom source/drain region, wherein the first field effect transistor (FET) stack includes a first vertical transport fin field effect transistor (VTFET) device between a second VTFET device and the first bottom source/drain region;

a second field effect transistor (FET) stack on a second bottom source/drain region, wherein the second field effect transistor (FET) stack includes a third VTFET device between a fourth VTFET device and the second bottom source/drain region, wherein the second bottom source/drain region is aligned with the first bottom source/drain region along a long axis;

a third field effect transistor (FET) stack on a third bottom source/drain region, wherein the third field effect transistor (FET) stack includes a fifth VTFET device between a sixth VTFET device and the third bottom source/drain region, wherein the third bottom source/drain region is laterally adjacent to the first bottom source/drain region and the second bottom source/drain region, and the third field effect transistor (FET) stack is positioned between the first field effect transistor (FET) stack and second field effect transistor (FET) stack;

a first electrical connection interconnecting a gate structure of the third VTFET device with a gate structure of the fifth VTFET device;

a second electrical connection interconnecting a gate structure of the second VTFET device with a gate structure of the sixth VTFET device; and

a ground electrically connected to the first bottom source/drain region and the second bottom source/drain region.

17. The memory device of claim 16 , further comprising a first shared source/drain region between the first VTFET device and the second VTFET device; a second shared source/drain region between the third VTFET device and the fourth VTFET device; and a third shared source/drain region between the fifth VTFET device and the sixth VTFET device.

18. The memory device of claim 17 , wherein the first VTFET device, second VTFET device, third VTFET device, and fourth VTFET device are each n-type VTFET devices, and the fifth VTFET device and sixth VTFET device are each p-type VTFET devices.

19. The memory device of claim 18 , further comprising a sixth electrical connection in electrical contact with the third shared source/drain region and electrically connected to a power rail, wherein the power rail is parallel to a long axis of the third field effect transistor (FET) stack.

20. The memory device of claim 19 , wherein the first shared source/drain region and the second shared source/drain region are each configured as drains, and the third shared source/drain region is configured as a source.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2021
From: KANG, TSUNG-SHENG; RAHMAN, ARDASHEIR; LI, TAO; YOUNG, ALBERT M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 056932/0001 →
Continuity (1)
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