Vertical access transistors and methods for forming the same
View Patent ↗A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.
1. A semiconductor structure comprising:
a two-dimensional array of vertical stacks located over a substrate, wherein each of the two-dimensional array of vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode;
active layers comprising a semiconducting metal oxide material and extending over sidewalls of a respective one of the vertical stacks;
gate dielectrics extending over a respective one of the active layers;
gate electrodes laterally surrounding, and overlying, a respective one of the gate dielectrics, laterally extending along the first horizontal direction, and laterally spaced apart along the second horizontal direction; and
a two-dimensional array of top contact via structures contacting a respective one of the top electrodes, and not in direct contact with any of the gate dielectrics.
2. The semiconductor structure of claim 1 , wherein, within each of the two-dimensional array of vertical stacks, a top periphery of the dielectric pillar coincides with a bottom periphery of the top electrode, and a top periphery of the bottom electrode is laterally offset outward from a bottom periphery of the dielectric pillar.
3. The semiconductor structure of claim 1 , wherein each of the active layers contacts top surfaces of a respective bottom electrodes.
4. The semiconductor structure of claim 1 , wherein each of the active layers contacts peripheral portions of top surfaces of a respective top electrode.
5. The semiconductor structure of claim 1 , further comprising dielectric wall structures laterally extending along the first horizontal direction between a respective neighboring pair of gate electrodes selected from the gate electrodes and vertically extending at least from a first horizontal plane including top surfaces of the top electrodes to a second horizontal plane including top surfaces of the gate electrodes.
6. The semiconductor structure of claim 1 , further comprising: a contact-level dielectric layer overlying the gate electrodes, the vertical stacks, and the active layers, wherein the two-dimensional array of top contact via structures vertically extends through the contact-level dielectric layer and is electrically isolated from the gate electrodes by a respective dielectric material portion overlying the respective one of the top electrodes.
7. The semiconductor structure of claim 1 , further comprising:
a two-dimensional array of bottom contact via structures contacting a bottom surface of a respective one of the bottom electrodes; and
bit lines contacting a respective column of the bottom contact via structures that are arranged along the second horizontal direction.
8. The semiconductor structure of claim 1 , wherein:
each column of the bottom electrodes that are arranged along the second horizontal direction is merged into a respective contiguous metal line to provide upper bit lines that laterally extend along the second horizontal direction; and
the semiconductor structure comprises lower bit lines that laterally extend along the second horizontal direction, underlie a respective one of the upper bit lines, and are electrically connected to the respective one of the upper bit lines by a respective column of bottom contact via structures.
9. The semiconductor structure of claim 1 , wherein each of the active layers comprises a horizontally-extending portion and a tubular portion laterally surrounding, and contacting, a respective vertical stack.
10. A semiconductor structure comprising:
a two-dimensional array of vertical stacks located over a substrate, wherein each of the two-dimensional array of vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode;
active layers extending over sidewalls of a respective one of the vertical stacks;
gate dielectrics extending over a respective one of the active layers;
gate electrodes laterally surrounding, and overlying, a respective one of the gate dielectrics; and
a two-dimensional array of top contact via structures contacting a respective one of the top electrodes, and not in direct contact with any of the gate dielectrics.
11. The semiconductor structure of claim 10 , wherein the active layers comprise a semiconducting metal oxide material.
12. The semiconductor structure of claim 10 , wherein each of the gate electrodes laterally extends along the first horizontal direction and laterally surrounds a respective row of vertical stacks within the two-dimensional array of vertical stacks.
13. The semiconductor structure of claim 10 , wherein each of the gate dielectrics laterally extends along the first horizontal direction and laterally surrounds a respective row of vertical stacks within the two-dimensional array of vertical stacks.
14. The semiconductor structure of claim 10 , wherein, within each of the two-dimensional array of vertical stacks, a top periphery of the dielectric pillar coincides with a bottom periphery of the top electrode, and a top periphery of the bottom electrode is laterally offset outward from a bottom periphery of the dielectric pillar.
15. The semiconductor structure of claim 10 , wherein each of the active layers contacts peripheral portions of top surfaces of a respective top electrode.
16. The semiconductor structure of claim 10 , further comprising dielectric wall structures laterally extending along the first horizontal direction between a respective neighboring pair of gate electrodes selected from the gate electrodes and vertically extending at least from a first horizontal plane including top surfaces of the top electrodes to a second horizontal plane including top surfaces of the gate electrodes.
17. The semiconductor structure of claim 10 , wherein:
each of the top contact via structures vertically extends through an opening in a respective one of the gate dielectrics.
18. The semiconductor structure of claim 10 , further comprising a contact-level dielectric layer overlying the gate electrodes, the vertical stacks, and the active layers, wherein the two-dimensional array of top contact via structures vertically extends through the contact-level dielectric layer and is electrically isolated from the gate electrodes by a respective dielectric material portion, and wherein the active layers comprise portions that protrude downward below a horizontal plane including horizontal interfaces between bottom surfaces of the bottom electrodes and an underlying insulating layer.
19. A semiconductor structure comprising:
a two-dimensional array of vertical stacks located over a substrate, wherein each of the two-dimensional array of vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode;
active layers extending over sidewalls of a respective one of the vertical stacks;
gate dielectrics extending over a respective row of vertical stacks within the two-dimensional array of vertical stacks, each row of vertical stacks being arranged along a first horizontal direction;
gate electrodes laterally surrounding vertically-extending portions of, and overlying horizontally-extending portions of, a respective one of the gate dielectrics; and
a two-dimensional array of top contact via structures contacting a respective one of the top electrodes, and not in direct contact with any of the gate dielectrics.
20. The semiconductor structure of claim 19 , further comprising:
a contact-level dielectric layer overlying the gate electrodes, the vertical stacks, and the active layers, wherein the two-dimensional array of top contact via structures vertically extends through the contact-level dielectric layer and is electrically isolated from the gate electrodes by a respective dielectric material portion overlying the respective one of the top electrodes;
a two-dimensional array of bottom contact via structures contacting a bottom surface of a respective one of the bottom electrodes; and
bit lines contacting a respective column of the bottom contact via structures that are arranged along the second horizontal direction.