System and method for modeling memory devices with latency
Systems and methods for emulate or prototyping of hardware, such as memory, are disclosed. A memory compiler may receive information, such as system calls, indicative of one or more aspects of latency. Responsive to the information, the memory compiler may create infrastructure, such as pipelines and FIFOs, based on the aspects of latency, for emulation or prototyping of the hardware. Using the created infrastructure may improve emulation compile speed, such as by creating a pipeline-based cache structure, and may improve emulation runtime speed, such as by utilizing earlier unused model clocks to fetch data from host sooner.
1 . A computer-implemented method for emulation or prototyping of a circuit design comprising:
responsive to receiving information regarding circuit design latency of the circuit design, generating, using a memory compiler, a memory model comprising infrastructure regarding the circuit design latency while reducing emulation or prototyping latency when performing the emulation or the prototyping of the circuit design, wherein, responsive to at least one memory access request comprising the information regarding the circuit design latency, creating the infrastructure regarding the circuit design latency based on the information regarding the circuit design latency; and
performing, using the memory model, one or both of the emulation or the prototyping of the circuit design.
2 . The method of claim 1 , wherein the information is based on the at least one memory access request indicative of the circuit design latency;
wherein performing the at least one memory access request results in the emulation or prototyping latency; and
wherein responsive to accessing the at least one memory access request, generating the memory model comprising the infrastructure reflective of the circuit design latency in the at least one memory access request and reducing the emulation or prototyping latency in performing the at least one memory access request.
3 . The method of claim 2 , wherein the circuit design latency is used to reduce the emulation or prototyping latency for another request system call; and
wherein the circuit design latency is indicative of a time at which a response to the at least one memory access request is expected.
4 . The method of claim 3 , wherein the time at which the response is expected is in a number of clock cycles;
wherein the memory compiler creates a FIFO infrastructure responsive to the at least one memory access request based on the circuit design latency; and
wherein the FIFO infrastructure delivers the response at a time based on a number of clock cycles indicative of when the request will mature.
5 . The method of claim 3 , wherein emulation or prototyping latency is due to fetching data for the another request system call; and
wherein the fetching of the data for the another request system call is performed at least partly during performing the at least one memory access request.
6 . The method of claim 1 , wherein the memory model performs at least one action related to the emulation or prototyping latency at least partly during the circuit design latency.
7 . The method of claim 6 , wherein the at least one action comprises fetching data.
8 . The method of claim 1 , wherein the information of latency comprises delay due to a cache miss.
9 . The method of claim 1 , wherein the information of latency in the at least one memory access request comprises on one or more fields in the at least one memory access request; and
wherein the infrastructure created is based on the one or more fields in the at least one memory access request.
10 . The method of claim 9 , wherein the one or more fields comprise a type of memory access.
11 . The method of claim 10 , wherein the type of the at least one memory access comprises one of read, write, burst read, or burst write.
12 . The method of claim 9 , wherein the one or more fields comprise at least one of:
a memory core declaration identifier;
cycle latency in one or more memory accesses; or
an address range to be accessed.
13 . A non-transitory machine-readable medium for emulation or prototyping of a circuit design comprising instructions that, when executed by a processor, cause a computing system to:
responsive to receiving information regarding circuit design latency of the circuit design, generate, use a memory compiler, a memory model comprising infrastructure regarding the circuit design latency while reducing emulation or prototyping latency when performing the emulation or the prototyping of the circuit design, wherein, responsive to at least one memory access request comprising the information regarding the circuit design latency, creating the infrastructure regarding the circuit design latency based on the information regarding the circuit design latency; and
perform, using the memory model, one or both of the emulation or the prototyping of the circuit design.
14 . The non-transitory machine-readable medium of claim 13 , wherein the information is based on the at least one memory access request indicative of the circuit design latency;
wherein performing the at least one memory access request results in the emulation or prototyping latency; and
wherein the instructions cause the computing system to, responsive to accessing the at least one memory access request, generate the memory model comprising the infrastructure reflective of the circuit design latency in the at least one memory access request and reducing the emulation or prototyping latency in performing the at least one memory access request.
15 . The non-transitory machine-readable medium of claim 14 , wherein the circuit design latency is used to reduce the emulation or prototyping latency for another request system call; and
wherein the circuit design latency is indicative of a time at which a response to the at least one memory access request is expected.
16 . The non-transitory machine-readable medium of claim 15 , wherein the time at which the response is expected is in a number of clock cycles;
wherein the memory compiler creates a FIFO infrastructure responsive to the at least one memory access request based on the circuit design latency; and
wherein the FIFO infrastructure delivers the response at a time based on a number of clock cycles indicative of when the request will mature.
17 . The non-transitory machine-readable medium of claim 13 , wherein the memory model performs at least one action related to the emulation or prototyping latency at least partly during the circuit design latency.
18 . The non-transitory machine-readable medium of claim 17 , wherein the at least one action comprises fetching data.
19 . The non-transitory machine-readable medium of claim 15 , wherein emulation or prototyping latency is due to fetching data for the another request system call; and
wherein the fetching of the data for the another request system call is performed at least partly during performing the at least one memory access request.