IP Library › Granted Patent US 12,232,429
Granted Patent B2
US 12,232,429 · App. 17/384,933 · Granted Feb 18, 2025

Semiconductor device including data storage material pattern

Inventors: Jeonghee Park (Hwaseong-si, KR); Dongho Ahn (Hwaseong-si, KR); Wonjun Park (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10N70/231H10B63/80H10N70/841H10N70/8828
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Quick Facts
Patent No.
US 12,232,429
App. No.
17/384,933
Granted
Feb 18, 2025
Kind
B2
Abstract

A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of In α Ge β Sb γ Te δ . In the phase change material layer of In α Ge β Sb γ Te δ , a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.

Claims (64)

1. A semiconductor device comprising:

a lower structure;

a first conductive line on the lower structure and extending in a first horizontal direction;

a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and

a memory cell structure between the first conductive line and the second conductive line, wherein

the memory cell structure includes a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction,

the data storage material pattern includes a phase change material layer of In α Ge β Sb γ Te δ and a first additional phase change material layer overlapping the phase change material layer of In α Ge β Sb γ Te δ ,

in the phase change material layer of In α Ge β Sb γ Te δ , a sum of α and β is lower than about 30 at. %, and a sum of γ and δ is higher than about 70 at. %, and

the first additional phase change material layer is a phase change material layer without In or a phase change material layer having a lower In content than the phase change material layer of In α Ge β Sb γ Te δ .

2. The semiconductor device of claim 1 , wherein, in the phase change material layer of In α Ge β Sb γ Te δ ,

the sum of α and β is equal to or lower than about 20 at. %, and

the sum of γ and δ is equal to or higher than about 80 at. %.

3. The semiconductor device of claim 2 , wherein

γ is about 30 at. %, and

δ is about 50 at. %.

4. The semiconductor device of claim 2 , wherein a is equal to or higher than about 10 at. % and equal to or lower than about 20 at. %.

5. The semiconductor device of claim 4 , wherein β is less than α.

6. The semiconductor device of claim 4 , wherein

the data storage material pattern further comprises an additional element, and

the additional element is at least one of B, Al, Ga, In, Tl, C, Si, Ge, Sn, N, P, As, Sb, Bi, O, S, Se, Te, Zn, Cd, W, Ti, Hf, or Zr.

7. The semiconductor device of claim 1 , wherein

the data storage material pattern further comprises a second additional phase change material layer,

the phase change material layer of In α Ge β Sb γ Te δ is between the first additional phase change material layer and the second additional phase change material layer,

the second additional phase change material layer is a phase change material layer without In or a phase change material layer having a lower In content than the phase change material layer of In α Ge β Sb γ Te δ .

8. The semiconductor device of claim 1 , wherein

the lower structure comprises a semiconductor substrate, a circuit device on the semiconductor substrate, and a lower insulating structure on the semiconductor substrate and covering the circuit device.

9. A semiconductor device comprising:

a lower structure including a semiconductor substrate, a circuit device on the semiconductor substrate, and a lower insulating structure on the semiconductor substrate and covering the circuit device; and

a plurality of memory cell structures on the lower structure and stacked in a vertical direction, wherein

the plurality of memory cell structures include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in the vertical direction, respectively,

the data storage material pattern includes a phase change material layer of In α Ge β Sb γ Te δ and an additional phase change material layer overlapping the phase change material layer of In α Ge β Sb γ Te δ , and

in the phase change material layer of In α Ge β Sb γ Te δ , a sum of α and β is lower than about 30 at. %, and a sum of γ and δ is higher than about 70 at. %, and

the additional phase change material layer is a phase change material layer without In or a phase change material layer having a lower In content than the phase change material layer of In α Ge β Sb γ Te δ .

10. The semiconductor device of claim 9 , wherein, in the phase change material layer of In α Ge β Sb γ Te δ ,

the sum of α and β is equal to or lower than about 20 at. %, and

the sum of γ and δ is equal to or higher than about 80 at. %.

11. The semiconductor device of claim 10 , wherein

γ is about 30 at. %, and

δ is about 50 at. %.

12. The semiconductor device of claim 10 , wherein a is equal to or higher than about 10 at. % and equal to or lower than about 20 at. %.

13. A semiconductor device comprising:

a lower structure including a row driver, a column driver, and a control logic electrically connected to the row driver and the column driver; and

an upper structure on the lower structure, wherein the upper structure includes a first conductive line on the lower structure, a second conductive line on the first conductive line, and a first memory cell structure between the first conductive line and the second conductive line;

a first contact structure electrically connecting the first conductive line to the row driver;

a second contact structure electrically connecting the second conductive line to the column driver; and

an input/output contact structure passing through the upper structure and extending into the lower structure, the input/output contact structure being electrically connected to the control logic, wherein

the first memory cell structure includes a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction,

the data storage material pattern includes a phase change material layer of In α Ge β Sb γ Te δ and an additional phase change material layer overlapping the phase change material layer of In α Ge β Sb γ Te δ ,

in the phase change material layer of In α Ge β Sb γ Te δ , a sum of α and β is lower than about 30 at. %, and a sum of γ and δ is higher than about 70 at. %,

the additional phase change material layer is a phase change material layer without In or a phase change material layer having a lower In content than the phase change material layer of In α Ge β Sb γ Te δ .

14. The semiconductor device of claim 13 , wherein

the first memory cell structure further comprises a lower electrode pattern between the first conductive line and the selector material pattern, an intermediate electrode pattern between the selector material pattern and the data storage material pattern, and an upper electrode pattern between the data storage material pattern and the second conductive line, and

in the phase change material layer of In α Ge β Sb γ Te δ , the sum of α and β is equal to or lower than about 20 at. %, and the sum of γ and δ is equal to or higher than about 80 at. %.

15. The semiconductor device of claim 14 , wherein

γ is about 30 at. %, and

δ is about 50 at. %.

16. The semiconductor device of claim 14 , wherein a is equal to or higher than about 10 at. % and equal to or lower than about 20 at. %.

17. The semiconductor device of claim 14 , wherein

the selector material pattern is a threshold switching element,

the first conductive line has a first thickness,

the second conductive line has a second thickness,

the second thickness is more than two times the first thickness and less than three times the first thickness,

the selector material pattern has a thickness of about 100 Å to about 200 Å, and

the data storage material pattern has a thickness of about 300 Å to about 450 Å.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2021
From: PARK, JEONGHEE; AHN, DONGHO; PARK, WONJUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 057045/0569 →
Priority Claims (1)
KR 10-2020-0118176 · Sep 15, 2020 · national
Continuity (1)
Related Publication 20220085286A1 · Mar 17, 2022
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