Memory and formation method thereof
A memory formation method includes: providing a substrate; forming a first mask layer on the substrate, in the first mask layer there being formed a plurality of parallel-arranged strip-shaped patterns positioned above the array area, and an end of each of the strip-shaped patterns being connected to the first mask layer on the peripheral area of the substrate; forming a second mask layer on the first mask layer, in the second mask layer there being formed a plurality of first patterns; and etching layer by layer by using the second mask layer and the first mask layer as masks to transfer the strip-shaped patterns and the first patterns into the substrate to form the discrete active areas arranged in an array.
1. A memory, comprising:
a substrate, comprising an array area and a peripheral area encircling the array area; and
a plurality of discrete active areas arranged in staggered rows and located in the array area; and, wherein
a first-positioned discrete active area, in each row of a first plurality of adjacent rows, contacts the substrate of the peripheral area at a first side of the array area;
a first-positioned discrete active area, in each row of a second plurality of adjacent rows, contacts the substrate of the peripheral area at a second side of the array area that intersects the first side of the array area; and
the discrete active areas are separated from each other by a shallow trench isolation structure;
wherein a last-positioned discrete active area, in each row of the first plurality of adjacent rows, contacts the substrate of the peripheral area; and
a last-positioned discrete active area, in each row of the second plurality of adjacent rows, contacts the substrate of the peripheral area.
2. The memory according to claim 1 , wherein
the first-positioned discrete active area, in each row of the first plurality of adjacent rows, contacts only the substrate of the peripheral area at the first side of the array area; and
the first-positioned discrete active area, in each row of the second plurality of adjacent rows, contacts only the substrate of the peripheral area at the second side of the array area.
3. The memory according to claim 1 , wherein all first-positioned discrete active areas in the staggered rows contact the substrate of the peripheral area; and/or all last-positioned discrete active areas in the staggered rows contact the substrate of the peripheral area.
4. The memory according to claim 1 , wherein:
every first-positioned discrete active area at the first side of the array area has a substantially equal longitudinal length; and
adjacent first-positioned discrete active areas at the second side of the array area have unequal longitudinal lengths.
5. The memory according to claim 4 , wherein the first-positioned discrete active areas at the second side of the array area vary cyclically in longitudinal length.
6. The memory according to claim 1 , wherein:
each medially positioned discrete active area, that does not contact the substrate of the peripheral area, has a substantially equal longitudinal length; and
in at least one row of the staggered rows, the first-positioned discrete active area has a shorter or longer longitudinal length than a medially positioned discrete active area that does not contact the substrate of the peripheral area.
7. The memory according to claim 1 , wherein a peripheral shallow trench isolation structure is formed in the substrate of the peripheral area and encircles the array area, and the peripheral shallow trench isolation structure is separated from the array area by the substrate of the peripheral area.
8. The memory according to claim 7 , wherein a sidewall of the peripheral shallow trench isolation structure facing toward a side of the array area is a curved surface.
9. The memory according to claim 7 , wherein each sidewall of the peripheral shallow trench isolation structure facing toward a respective side of the array area is a curved surface.
10. The memory according to claim 1 , wherein the shallow trench isolation structure comprises a plurality of parallel strip-shaped first shallow trench isolation structures and a plurality of staggered block-shaped second shallow trench isolation structures, the array area being divided by the plurality of first shallow trench isolation structures into a plurality of strip-shaped continuous active areas arranged in parallel, and the plurality of strip-shaped continuous active areas being divided by the plurality of second shallow trench isolation structures into the plurality of discrete active areas.
11. The memory according to claim 10 , wherein end surfaces of the first shallow trench isolation structures on a same side of the array area are flush with each other.
12. The memory according to claim 10 , wherein:
each of the first shallow trench isolation structures contacts the substrate of the peripheral area; and
none of the second shallow trench isolation structures contacts the substrate of the peripheral area.