Via structures
A device includes a substrate having a top surface, a fin extending lengthwise along a first direction, a source feature and a drain feature, a gate structure having a gate stack extending along a second direction perpendicular to the first direction and interposing between the source and drain features, a gate via directly disposed on the gate stack, a source via electrically connecting the source feature, and a drain via electrically connecting the drain feature. The fin includes a stack of channel layers engaged by the gate stack. The source via has a first dimension along the second direction and a second dimension along the first direction, the drain via feature has a third dimension along the second direction and a fourth dimension along the first direction. A ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.
1. A semiconductor device, comprising:
a substrate;
a stack of channel layers disposed over the substrate and extending lengthwise along a first direction;
a source feature and a drain feature disposed over the substrate, wherein the stack of channel layers extend between the source feature and the drain feature;
a gate structure disposed over the substrate and extending along a second direction perpendicular to the first direction, wherein the gate structure is disposed between the source feature and the drain feature and the gate structure has a gate stack that engages the stack of channel layers;
a gate via disposed directly on the gate stack;
a source via connected to the source feature; and
a drain via connected to the drain feature, wherein:
the source via has a first dimension along the second direction and a second dimension along the first direction,
the drain via has a third dimension along the second direction and a fourth dimension along the first direction,
a ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension,
the gate via has a fifth dimension along the second direction and a sixth dimension along the first direction,
the fifth dimension is less than the third dimension and the sixth dimension is less than the fourth dimension,
the ratio of the first dimension to the second dimension is greater than a ratio of the fifth dimension to the sixth dimension, and
the gate stack has a gate stack width along the first direction, wherein the gate stack width is greater than the sixth dimension.
2. The semiconductor device of claim 1 , wherein:
the gate via has a first top cross-sectional area;
the source via has a second top cross-sectional area;
the drain via has a third top cross-sectional area;
the first top cross-sectional area is less than the third top cross-sectional area; and
the third top cross-sectional area is less than the second top cross-sectional area.
3. The semiconductor device of claim 2 , wherein:
a ratio of the second top cross-sectional area to the third top cross-sectional area is about 1.15:1 to about 10:1, and
a ratio of the third top cross-sectional area to the first top cross-sectional area is about 1.1:1 to about 3:1.
4. The semiconductor device of claim 1 , further comprising:
a first metal line having a first line width along the second direction, wherein:
the source via is connected to the first metal line, and
the source via is disposed between the source feature and the first metal line; and
a second metal line having a second line width along the second direction, wherein:
the drain via is connected to the second metal line,
the drain via is disposed between the drain feature and the second metal line, and
a ratio of the first line width to the second line width is about 1.3:1 to about 10:1.
5. The semiconductor device of claim 1 , wherein the gate via overlaps an edge of the stack of channel layers.
6. The semiconductor device of claim 1 , wherein the gate via overlaps the stack of channel layers.
7. The semiconductor device of claim 6 , wherein:
the stack of channel layers is a first stack of channel layers,
the gate via is a first gate via,
the semiconductor device further comprises a second stack of channel layers and a second gate via, and
the second gate via does not overlap the second stack of channel layers.
8. The semiconductor device of claim 1 , wherein:
the ratio of the first dimension to the second dimension is about 1.2 to about 10; and
the ratio of the third dimension to the fourth dimension is about 1 to about 1.2.
9. The semiconductor device of claim 1 , wherein:
the stack of channel layers is a first stack of channel layers,
the semiconductor device further comprises a second stack of channel layers, and
the gate via overlaps one of the first stack of channel layers or the second stack of channel layers.
10. The semiconductor device of claim 1 , further comprising:
a source contact disposed between and connecting the source via to the source feature, wherein the source contact extends along the second direction; and
a drain contact disposed between and connecting the drain via to the drain feature, wherein the drain contact extends along the second direction.
11. The semiconductor device of claim 1 , wherein:
the stack of channel layers, the source feature, the drain feature, and the drain via are within a first memory cell,
the source feature is a first source feature,
the semiconductor device further comprises a second memory cell comprising a second source feature,
the source via is connected to the source feature and the second source feature, and
the source via is disposed over a boundary between the first memory cell and the second memory cell.
12. The semiconductor device of claim 1 , wherein the ratio of the first dimension to the second dimension is about 1.2:1 to about 10:1.
13. A semiconductor device, comprising:
a substrate;
a first gate structure and a second gate structure on the substrate extending along a gate direction, wherein each of the first gate structure and the second gate structure has a respective gate stack and respective gate spacers along sidewalls of the respective gate stack;
a first source feature, a second source feature, and a common drain feature, wherein the first gate structure is disposed between the first source feature and the common drain feature and the second gate structure is disposed between the common drain feature and the second source feature;
first semiconductor layers disposed between the first source feature and the common drain feature, wherein the first gate structure wraps the first semiconductor layers;
second semiconductor layers disposed between the common drain feature and the second source feature, wherein the second gate structure wraps the second semiconductor layers;
a first source via connected to the first source feature;
a second source via connected to the second source feature;
a drain via connected to the common drain feature;
a first gate via connected to the respective gate stack of the first gate structure; and
a second gate via connected to the respective gate stack of the second gate structure;
wherein:
each of the first source via and the second source via has a first top surface area,
the drain via has a second top surface area,
each of the first gate via and the second gate via has a third top surface area,
the first top surface area is greater than the second top surface area,
the second top surface area is greater than the third top surface area,
the first gate via is disposed directly over and overlaps the first semiconductor layers, and
the second gate via is directly disposed over an isolation region and does not overlap the second semiconductor layers.
14. The semiconductor device of claim 13 , wherein:
a ratio of the first top surface area to the second top surface area is about 1.15:1 to about 10:1, and
a ratio of the second top surface area to the third top surface area is about 1.1:1 to about 3:1.
15. The semiconductor device of claim 13 , further comprising:
a first source contact and a second source contact, wherein:
the first source contact is disposed between the first source via and the first source feature,
the second source contact is disposed between the second source via and the second source feature, and
the first source contact and the second source contact extend lengthwise along the gate direction; and
a drain contact, wherein;
the drain contact is disposed between the drain via and the common drain feature, and
the drain contact extends lengthwise along the gate direction.
16. The semiconductor device of claim 13 , wherein the first source via, the second source via, the drain via, the first gate via, and the second gate via are ruthenium (Ru) vias.
17. The semiconductor device of claim 13 , wherein the first source via has a first dimension along the gate direction and a second dimension along a first direction perpendicular to the gate direction.
18. The semiconductor device of claim 17 , wherein the drain via has a third dimension along the gate direction and a fourth dimension along the first direction.
19. The semiconductor device of claim 18 , wherein a ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.
20. The semiconductor device of claim 18 , wherein:
the gate via has a fifth dimension along the gate direction and a sixth dimension along the first direction, and
the fifth dimension is less than the third dimension and the sixth dimension is less than the fourth dimension.