CMOS compatible low-resistivity Al—Sc metal etch stop
View Patent ↗An aluminum-scandium (Al—Sc) etch stop that is both CMOS compatible and highly conductive, and a method for forming the same are disclosed. The low volatility of Sc in Cl and strong covalent bond between Al—Sc leads to an increase in resistance to NaCl corrosion and makes it difficult to dry etch in Cl-based chemistries, resulting in an excellent etch stop material, especially when used in conjunction with an overlying aluminum nitride (AlN) or aluminum scandium nitride (AlScN) piezoelectric layer. When deposited at high deposition temperatures or when subsequently annealed at >600° C., the Al—Sc has a low resistivity, enabling corresponding device operation at temperatures up to at least 500° C. While Al 3 Sc is the preferred composition, Al 1-x Sc x with x between 5 and 100 atomic percent provides many of these same benefits but comes at the cost of increased electrical resistivity and etch resistance with increasing Sc content due to Sc oxidation.
1. A semiconductor device comprising:
a substrate;
an adhesion promoting layer on the substrate;
a layer comprising 80% Al 3 Sc on the adhesion promoting layer, the layer comprising 80% Al 3 Sc having a crystallographic orientation of 111, the crystallographic orientation due to the adhesion promoting layer; and
an active layer on the layer comprising 80% Al 3 Sc.
2. The semiconductor device of claim 1 , wherein the substrate includes one of a semiconductor wafer, a processed semiconductor wafer, an in-process semiconductor wafer, a composite wafer, or a cavity SOI wafer.
3. The semiconductor device of claim 1 , wherein a thickness of the layer comprising 80% Al 3 Sc is between approximately 10 nm and approximately 10,000 nm.
4. The semiconductor device of claim 1 , wherein the layer comprising 80% Al 3 Sc has a resistivity of approximately 150 μΩ-cm or less.
5. The semiconductor device of claim 4 , wherein the layer comprising 80% Al 3 Sc has a resistivity of approximately 20 μΩ-cm or less.
6. The semiconductor device of claim 1 , wherein the layer comprising 80% Al 3 Sc further includes:
a layer of Sc.
7. The semiconductor device of claim 1 , wherein the layer comprising 80% Al 3 Sc has a sloped-sidewall with an angle of approximately 10° to approximately 35° from a normal to a plane of the layer comprising 80% Al 3 Sc.
8. The semiconductor device of claim 1 , wherein the adhesion promoting layer includes at least one of AlN, Al 1-x Sc x N, Al x Ga 1-x N, GaN, NbN, sapphire, Sc, SiN, Ta, TaN, Ti, TiN, or W.
9. The semiconductor device of claim 1 , wherein a thickness of the adhesion promoting layer is between approximately 10 nm and approximately 150 nm.
10. The semiconductor device of claim 1 ,
wherein the active layer includes Al 1-x Sc x N; and
wherein x is between 0.0 at. % and approximately 45 at. %.
11. The semiconductor device of claim 1 , wherein the active layer includes at least one of Si, SiN, GaN, AlN, Al x Ga 1-x N, AlScN, or sapphire.
12. The semiconductor device of claim 1 , wherein the active layer includes at least one of SiO 2 , Si 3 N 4 , AlN, or a doped or undoped silicate glass.
13. The semiconductor device of claim 1 , wherein at least a portion of the active layer has been removed down to the layer comprising 80% Al 3 Sc.
14. The semiconductor device of claim 1 , wherein the layer comprising 80% Al 3 Sc is adapted to resist plastic deformation induced by heating of the semiconductor device.
15. The semiconductor device of claim 1 , wherein the semiconductor device is adapted to operate at temperatures up to at least 500° C.