Memory device and memory system including the same

1. A memory device, comprising:

a memory cell array including memory cells arranged in a plurality of rows;

an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data;

a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and

a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate one of a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

2. The memory device as claimed in claim 1 , wherein the flag generator includes:

a comparator configured to compare the read row address with the fail row address, and to output a comparison signal, and

a signal generator configured to generate one of the decoding state flag and the fail row flag based on the comparison signal.

3. The memory device as claimed in claim 1 , wherein:

the flag generator is configured to generate the fail row flag when the read row address and the fail row address are the same, and

the flag generator is configured to generate the decoding state flag when the read row address and the fail row address are not the same.

4. The memory device as claimed in claim 3 , wherein:

the ECC engine is configured to generate a first syndrome of the error in the first data, and

the flag generator is configured to generate the decoding state flag based on a value obtained by counting the first error occurrence signal and the first syndrome, when the read row address and the fail row address are not the same.

5. The memory device as claimed in claim 3 , wherein:

the ECC engine is configured to generate a first syndrome of the error in the first data, and

the flag generator is configured to generate the fail row flag regardless of the first syndrome and the first error occurrence signal, when the read row address and the fail row address are the same.

6. The memory device as claimed in claim 1 , wherein:

the ECC engine is configured to, for a section in which a refresh operation of the plurality of rows is performed,

detect an error in second data that is read from the memory cell array indicated by a scrubbing row address among the plurality of rows,

output a second error occurrence signal, and

perform a scrubbing operation to correct the error in the second data, and write error-corrected second data to the memory cell array indicated by the scrubbing row address, and

the row fail detector is configured to output whether the scrubbing row address is a fail row address based on the second error occurrence signal.

7. The memory device as claimed in claim 6 , wherein:

the ECC engine is configured to generate a second syndrome of the error in the second data, and

the row fail detector is configured to count the second error occurrence signal, and output the scrubbing row address as the fail row address based on a value obtained by counting the second error occurrence signal and the second syndrome.

8. The memory device as claimed in claim 6 , wherein:

the ECC engine is configured to perform the scrubbing operation for each of the plurality of rows, and to generate a first syndrome of the error in the first data,

the ECC engine is configured to count the second error occurrence signals output in each of the scrubbing operations,

the ECC engine further includes a control logic configured to compare a value obtained by counting the second error occurrence signal with a second threshold, and to output a comparison signal,

the flag generator is configured to generate the decoding state flag based on the first error occurrence signal and the first syndrome, when the read row address and the fail row address are the same, and

the flag generator is configured to generate the decoding state flag based on the first error occurrence signal, the first syndrome, and the comparison signal, when the read row address and the fail row address are not the same.

9. The memory device as claimed in claim 8 , wherein:

the flag generator is configured to generate the decoding state flag based on the first syndrome and the first error occurrence signal such that:

the decoding state flag has a first value that indicates that no error is detected, and

the decoding state flag has a second value that indicates that an error is detected and corrected,

the decoding state flag has a third value that indicates that two or more errors are detected and not corrected, and

based on the comparison signal, when the read row address and the fail row address are not the same, the decoding state flag having the second value is not generated.

10. The memory device as claimed in claim 9 , wherein the flag generator is configured to generate the decoding state flag having the first value or generate the decoding state flag having the third value, when:

the read row address and the fail row address are not the same, and

the comparison signal indicates that the value obtained by counting the second error occurrence signal is less than to the second threshold.

11. The memory device as claimed in claim 1 , wherein the row fail detector is configured to detect the fail row address for each section in which a refresh operation of the plurality of rows is performed.

12. A memory device, comprising:

a memory cell array including memory cells arranged in a plurality of rows;

an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output an error occurrence signal and a syndrome of the error in the first data, and to correct the error in the first data;

a row fail detector configured to periodically detect a fail row address, which indicates a fail row among the plurality of rows; and

a flag generator configured to compare a read row address included in the read address with the fail row address, generate a fail row flag, which indicates that the read row address is a fail row address, when the read row address and the fail row address are the same, and generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, based on the syndrome and the error occurrence signal, when the read row address and the fail row address are not the same.

13. The memory device as claimed in claim 12 , wherein the row fail detector is configured to detect the fail row address in a section in which a refresh operation of the plurality of rows is performed in response to a refresh command.

14. The memory device as claimed in claim 13 , wherein:

the ECC engine is configured to, after the refresh operation of the plurality of rows is performed in response to the refresh command, detect an error in second data that is read from the memory cell array, generate a second error occurrence signal, perform a scrubbing operation that corrects the error in the second data, and write error-corrected second data to the memory cell array, and

the row fail detector is configured to count the second error occurrence signal to detect the fail row address.

15. The memory device as claimed in claim 14 , wherein the flag generator is configured to generate the decoding state flag based on a value of the counted second error occurrence signal, and to generate the fail row flag regardless of the value of the counted second error occurrence signal.

16. The memory device as claimed in claim 12 , further comprising:

a first pin, which is configured to send and receive data; and

a second pin, which is configured to output the fail row flag or the decoding state flag, and which is different from the first pin.

17. The memory device as claimed in claim 16 , wherein:

the second pin includes a first sub-pin and a second sub-pin different from each other, and

the decoding state flag and the fail row flag are made up of two bits, and are output through the first sub-pin and the second sub-pin.

18. A memory system, comprising:

a memory device; and

a memory controller configured to provide a read command and a read address to the memory device, wherein:

the memory device includes:

a memory cell array including memory cells arranged in a plurality of rows,

an ECC engine configured to detect an error in first data that is read from the memory cell array in response to the read command and the read address, to output a first error occurrence signal, and to correct the error in the first data,

a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows, and

a flag generator configured to generate a decoding state flag and a fail row flag based on the read address, the first error occurrence signal, and the fail row address,

the fail row flag is made up of two bits and has a first value, and

the decoding state flag is made up of two bits and has any one of second, third, and fourth values that are each different from the first value and different from each other.

19. The memory system as claimed in claim 18 , wherein the memory controller is configured to receive one of the fail row flag and the decoding state flag, and to determine an error management policy of the memory device.

20. The memory system as claimed in claim 19 , wherein the memory controller is configured to determine the error management policy so as not to use the read address when receiving the fail row flag having the first value.