Method of writing data in nonvolatile memory device, nonvolatile memory device performing the same and method of operating memory system using the same
In a method of writing data in a nonvolatile memory device, a write command, a write address and write data to be programmed are received. Offset information representing a verification level is received. The offset information is provided when the write data corresponds to a distribution deterioration pattern by checking an input/output (I/O) pattern of the write data. When the offset information is received, the write data is programmed based on the offset information such that at least one state among a plurality of states included in a distribution of threshold voltages of memory cells in which the write data is stored is changed.
1. A method of writing data in a nonvolatile memory device, the method comprising:
receiving a write command, a write address and write data to be programmed;
receiving offset information representing a verification level, the receiving the offset information including,
checking an input/output (I/O) pattern of the write data and determining whether the write data corresponds to a distribution deterioration pattern based on results of the checking the I/O pattern of the write data,
in response to the write data not corresponding to the distribution deterioration pattern, not receiving the offset information, and
in response to the offset information not being received, programming the write data such that all of a plurality of states are maintained, the plurality of states corresponding to a distribution of threshold voltages of memory cells; and
in response to the offset information being received, programming the write data based on the offset information such that at least one state among the plurality of states included in the distribution of threshold voltages of memory cells in which the write data is stored is changed.
2. The method of claim 1 , wherein the distribution deterioration pattern includes a first deterioration pattern associated with data retention characteristic and a second deterioration pattern associated with read disturbance characteristic.
3. The method of claim 2 , wherein:
in response to the write data being write cold data that is written less than a first number of times, the write data is determined to correspond to the first deterioration pattern, and
in response to the write data being read hot data that is read more than a second number of times, the write data is determined to correspond to the second deterioration pattern.
4. The method of claim 2 , wherein:
the plurality of states include a first state through an N-th state, where N is a natural number greater than or equal to two,
the first state corresponds to a lowest voltage level, and the N-th state corresponds to a highest voltage level,
in response to the write data corresponding to the first deterioration pattern, the write data is programmed such that an interval between an (N−1)-th state and the N-th state increases, and
in response to the write data corresponding to the second deterioration pattern, the write data is programmed such that an interval between the first state and a second state increases.
5. The method of claim 1 , wherein the receiving the offset information includes:
detecting the I/O pattern of the write data;
determining whether to change the verification level based on the write data corresponding to the distribution deterioration pattern; and
in response to results of the determining indicating the write data corresponds to the distribution deterioration pattern, selecting an improved verification level; and
generating and providing the offset information including the improved verification level.
6. The method of claim 5 , wherein the I/O pattern of the write data is detected based on the write address.
7. The method of claim 5 , wherein the I/O pattern of the write data is detected based on a number of times the write data is accessed.
8. The method of claim 5 , wherein the improved verification level is selected based on a desired look-up table (LUT).
9. The method of claim 8 , further comprising:
updating the LUT used to select the improved verification level in real time.
10. The method of claim 5 , wherein receiving the offset information further includes:
storing the improved verification level.
11. The method of claim 1 , wherein:
the plurality of states includes a first state through an N-th state, where N is a natural number greater than or equal to two,
the first state corresponds to a lowest voltage level, and the N-th state corresponds to a highest voltage level, and
the programming the write data includes:
changing an N-th verification level among a first verification level through the N-th verification level based on the offset information such that the N-th state is changed, the first verification level through the N-th verification level corresponding to the first state through the N-th state, respectively; and
performing a program loop once or more on the write data based on the first verification level through the N-th verification level including the changed N-th verification level.
12. The method of claim 11 , wherein the N-th verification level increases, and an interval between an (N−1)-th state and the N-th state increases.
13. The method of claim 11 , wherein the programming the write data further includes:
additionally changing at least one of the first verification level through an (N−1)-th verification level based on the offset information.
14. The method of claim 13 , wherein an entire width of the distribution of threshold voltages is maintained in response to at least one of the first verification level through the N-th verification level being changed.
15. The method of claim 1 , wherein:
the plurality of states includes a first state through an N-th state, where N is a natural number greater than or equal to two,
the first state corresponds to a lowest voltage level, and the N-th state corresponds to a highest voltage level, and
the programming the write data includes:
changing a first verification level among the first verification level through an N-th verification level based on the offset information such that the first state is changed, the first verification level through the N-th verification level corresponding to the first state through the N-th state, respectively; and
performing a program loop once or more on the write data based on the first verification level through the N-th verification level including the changed first verification level.
16. The method of claim 15 , wherein the first verification level decreases, and an interval between the first state and a second state increases.
17. The method of claim 15 , wherein
additionally changing at least one of a second verification level through the N-th verification level based on the offset information.
18. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells; and
processing circuitry configured to,
receive a write command, a write address and write data to be programmed,
receive offset information representing a verification level, the receiving the offset information including,
checking an input/output (I/O) pattern of the write data and determining whether the write data corresponds to a distribution deterioration pattern based on results of the checking the I/O pattern of the write data,
in response to the write data not corresponding to the distribution deterioration pattern, not receiving the offset information, and
in response to the offset information not being received, programming the write data such that all of a plurality of states are maintained, the plurality of states corresponding to a distribution of threshold voltages of memory cells, and
program the write data based on the offset information in response to the offset information being received such that at least one state among the plurality of states included in the distribution of threshold voltages of memory cells in which the write data is stored is changed.
19. A method of operating a memory system including a memory controller and a nonvolatile memory device, the method comprising:
transmitting, by the memory controller, a write command, a write address and write data to be programmed to the nonvolatile memory device;
detecting, by the memory controller, an input/output (I/O) pattern of the write data;
selecting, by the memory controller, an improved verification level in response to a determination that the write data is write cold data or read hot data, the write cold data being data that is written less than a first number of times, the read hot data being data that is read more than a second number of times;
generating, by the memory controller, offset information including the improved verification level;
transmitting, by the memory controller, the offset information to the nonvolatile memory device;
changing, by the nonvolatile memory device, at least one of a first verification level through an N-th verification level based on the offset information, the first verification level through the N-th verification level corresponding to a first state through an N-th state, respectively, that are included in a distribution of threshold voltages; and
performing, by the nonvolatile memory device, a program loop once or more on the write data based on the first verification level through the N-th verification level such that at least one state among the first state through the N-th state is changed,
wherein the first state corresponds to a lowest voltage level, and the N-th state corresponds to a highest voltage level,
wherein, in response to the write data being the write cold data, the at least one state is changed such that an interval between an (N−1)-th state and the N-th state increases, and
wherein, in response to the write data being the read hot data, the at least one state is changed such that an interval between the first state and a second state increases.