Scalable Circuit-Under-Pad device topologies for lateral GaN power transistors
Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise source, drain and gate finger electrodes on active regions of a plurality of sections of a multi-section transistor, and a contact structure comprising source and drain contact areas, e.g. drain and source pads extending over active regions of each section, interconnected by conductive micro-vias to respective underlying drain and source finger electrodes. Alternatively, source contact areas comprise parts of a source bus which runs over inactive regions. For reduced gate loop inductance, the source bus may be routed over or under the to gate bus. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of the drain finger electrodes. Example CUP device structures provide for higher current carrying capability and reduced drain-source resistance.
1 . A semiconductor device structure comprising:
a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multi-section transistor;
each transistor section comprising source, drain and gate electrodes defined on an active region;
a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas;
the drain contact area comprising a drain pad extending over a central part of the active region located between the first and second source contact areas;
the drain pad being interconnected by conductive micro-vias to underlying parts of the drain electrodes and the first and second source contact areas being interconnected to the source electrodes; and
the first and second source contact areas being first and second parts of a source bus, the first and second parts of the source bus being located each side of the drain pad and the source bus being routed over inactive regions adjacent the active region.
2 . The semiconductor device structure of claim 1 , further comprising a gate bus interconnecting gate electrodes of each section, the gate bus being routed over said inactive regions, and the source bus being routed over or under the gate bus.
3 . The semiconductor device structure of claim 2 , wherein the drain pad has an area which is larger than an area of the first and second parts of the source bus.
4 . The semiconductor device structure of claim 3 , wherein the drain electrodes have a first cross-section and the source electrodes have a second cross-section greater than the first cross-section, and wherein said area of the drain pad and first and second parts of the source bus are sized in proportion to said first and second cross-sections.
5 . A semiconductor device structure comprising:
a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multi-section transistor;
each transistor section comprising source, drain and gate electrodes defined on an active region;
on-chip metallization defining for each section a contact structure comprising a drain pad a source bus, and a gate bus;
the drain pad extending over a central part of the active region, the drain pad being interconnected by conductive micro-vias to underlying parts of the drain electrodes;
the source bus being routed over inactive regions adjacent the active region, without extending over the active region;
the source bus comprising first and second parts each side of the drain pad, the source electrodes being connected to the first and second parts of the source bus;
and the gate bus being routed over said inactive regions and interconnecting the gate electrodes; and
the source bus overlapping the gate bus, running over or under the gate bus.