Phase-locked loop circuit, corresponding radar sensor, vehicle and method of operation
A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.
1. A circuit, comprising:
a tunable resonant circuit comprising:
a first node;
a second node;
an inductance coupled between said first node and said second node;
a variable capacitance coupled between said first node and said second node;
a set of capacitances selectively coupleable between said first node and said second node; and
a control node coupled to said variable capacitance, the control node configured to receive a control signal, wherein said tunable resonant circuit is tunable as a function of said control signal;
a biasing circuit coupled to said tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable-frequency output signal between said first node and said second node;
a phase-frequency detector circuit sensitive to an input reference signal and to said variable-frequency output signal, and configured to generate a first digital control signal and a second digital control signal as a function of a timing offset of said variable-frequency output signal with respect to said input reference signal, wherein assertion of said first digital control signal is indicative of a first operational state where said timing offset has a first sign, and wherein assertion of said second digital control signal is indicative of a second operational state where said timing offset has a second sign opposite said first sign;
a charge pump circuit and a filter circuit configured to generate said control signal to the control node as a function of said first digital control signal and said second digital control signal;
a timer circuit sensitive to a reset signal and configured to generate a timing signal, wherein said timing signal is asserted in response to a pulse sensed in said reset signal and said timing signal is de-asserted after a time interval from said sensed pulse; and
a calibration circuit configured to selectively couple, between said first node and said second node, selected capacitances from said set of capacitances, said selected capacitances being selected as a function of said second digital control signal, said calibration circuit performing the selective coupling in response to said timing signal being asserted.
2. The circuit of claim 1 , wherein said biasing circuit is configured to generate said variable-frequency output signal comprising frequency sweeps separated by dead times, and generate pulses in said reset signal at a beginning of said dead times.
3. The circuit of claim 1 , further comprising a switch configured to selectively couple said control node to a reference control voltage in response to said timing signal being asserted.
4. The circuit of claim 1 , comprising:
a feedback loop configured to provide said variable-frequency output signal to said phase-frequency detector circuit, wherein the feedback loop comprises a frequency divider circuit;
a voltage divider network configured to generate a set of different reference control voltages; and
a set of switches configured to selectively couple said control node to a respective reference control voltage in said set of different reference control voltages as a function of a divider programming word of said frequency divider circuit.
5. The circuit of claim 1 , wherein said calibration circuit is configured to count a number of pulses occurring in said second digital control signal and to couple, between said first node and said second node, a capacitance from said set of capacitances in response to a counted number of pulses in said second digital control signal reaching a threshold value.
6. The circuit of claim 5 , wherein said calibration circuit comprises a digital counter circuit configured to count said number of pulses occurring in said second digital control signal.
7. The circuit of claim 5 , wherein said calibration circuit comprises:
a further charge pump circuit configured to generate a pulsed current signal as a function of said first digital control signal and said second digital control signal;
an integrator circuit configured to generate a signal indicative of a value of an integral over time of said pulsed current signal; and
a comparator circuit configured to compare said signal indicative of a value of an integral over time of said pulsed current signal to a threshold voltage to detect said counted number of pulses in said second digital control signal reaching said threshold value.
8. A radar sensor, comprising:
a circuit comprising:
a tunable resonant circuit having a first node and a second node, and comprising:
an inductance coupled between said first node and said second node;
a variable capacitance coupled between said first node and said second node;
a set of capacitances selectively coupleable between said first node and said second node; and
a control node coupled to said variable capacitance, the control node configured to receive a control signal, wherein said tunable resonant circuit is tunable as a function of said control signal;
a biasing circuit coupled to said tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable-frequency output signal between said first node and said second node;
a phase-frequency detector circuit sensitive to an input reference signal and to said variable-frequency output signal, and configured to generate a first digital control signal and a second digital control signal as a function of a timing offset of said variable-frequency output signal with respect to said input reference signal, wherein assertion of said first digital control signal is indicative of a first operational state where said timing offset has a first sign, and wherein assertion of said second digital control signal is indicative of a second operational state where said timing offset has a second sign opposite said first sign;
a charge pump circuit and a filter circuit configured to generate said control signal to the control node as a function of said first digital control signal and said second digital control signal;
a timer circuit sensitive to a reset signal and configured to generate a timing signal, wherein said timing signal is asserted in response to a pulse sensed in said reset signal and said timing signal is de-asserted after a time interval from said sensed pulse; and
a calibration circuit configured to selectively couple, between said first node and said second node, selected capacitances from said set of capacitances, said selected capacitances being selected as a function of said second digital control signal, said calibration circuit performing the selective coupling in response to said timing signal being asserted; and
a transmitter circuit coupled to an antenna;
wherein the circuit is further configured to receive said input reference signal from a microcontroller unit and provide said variable-frequency output signal to said transmitter circuit.
9. A vehicle comprising the radar sensor according to claim 8 .
10. The radar sensor of claim 8 , wherein said biasing circuit is configured to generate said variable-frequency output signal comprising frequency sweeps separated by dead times, and generate pulses in said reset signal at a beginning of said dead times.
11. The radar sensor of claim 8 , further comprising a switch configured to selectively couple said control node to a reference control voltage in response to said timing signal being asserted.
12. The radar sensor of claim 8 , comprising:
a feedback loop configured to provide said variable-frequency output signal to said phase-frequency detector circuit, wherein the feedback loop comprises a frequency divider circuit;
a voltage divider network configured to generate a set of different reference control voltages; and
a set of switches configured to selectively couple said control node to a respective reference control voltage in said set of different reference control voltages as a function of a divider programming word of said frequency divider circuit.
13. The radar sensor of claim 8 , wherein said calibration circuit is configured to count a number of pulses occurring in said second digital control signal and to couple, between said first node and said second node, a capacitance from said set of capacitances in response to a counted number of pulses in said second digital control signal reaching a threshold value.
14. The radar sensor of claim 13 , wherein said calibration circuit comprises a digital counter circuit configured to count said number of pulses occurring in said second digital control signal.
15. The radar sensor of claim 13 , wherein said calibration circuit comprises:
a further charge pump circuit configured to generate a pulsed current signal as a function of said first digital control signal and said second digital control signal;
an integrator circuit configured to generate a signal indicative of a value of an integral over time of said pulsed current signal; and
a comparator circuit configured to compare said signal indicative of a value of an integral over time of said pulsed current signal to a threshold voltage to detect said counted number of pulses in said second digital control signal reaching said threshold value.
16. A method of operating a circuit, the method comprising:
biasing a tunable resonant circuit to generate a variable-frequency output signal between a first node and a second node;
generating a first digital control signal and a second digital control signal as a function of an input reference signal and said variable-frequency output signal, wherein said first digital control signal being asserted is indicative of a first operational state wherein a timing offset of said variable-frequency output signal with respect to said input reference signal has a first sign and wherein said second digital control signal being asserted is indicative of a second operational state wherein said timing offset has a second sign opposite said first sign;
generating a control signal as a function of said first digital control signal and said second digital control signal;
receiving said control signal at a control node coupled to a variable capacitance and tuning said tunable resonant circuit as a function of said control signal,
sensing a reset signal and generating a timing signal, wherein said timing signal is asserted in response to a pulse sensed in said reset signal and de-asserted after a time interval from said sensed pulse; and
selectively coupling, between said first node and said second node, selected capacitances from said set of capacitances as a function of said second digital control signal, in response to said timing signal being asserted.
17. The method of claim 16 , wherein said variable-frequency output signal is generated by biasing the tunable resonant circuit to perform frequency sweeps separated by dead times, and generate pulses in said reset signal at a beginning of said dead times.
18. The method of claim 16 , further comprising selectively coupling said control node to a reference control voltage in response to said timing signal being asserted.
19. The method of claim 10 , further comprising counting a number of pulses occurring in said second digital control signal and coupling, between said first node and said second node, a capacitance from said set of capacitances in response to a counted number of pulses in said second digital control signal reaching a threshold value.
20. The method of claim 19 , wherein a calibration circuit comprises a digital counter circuit configured to count said number of pulses occurring in said second digital control signal.
21. The method of claim 20 , further comprising:
generating a pulsed current signal as a function of said first digital control signal and said second digital control signal;
generating a signal indicative of a value of an integral over time of said pulsed current signal; and
comparing said signal indicative of a value of an integral over time of said pulsed current signal to a threshold voltage to detect said counted number of pulses in said second digital control signal reaching said threshold value.